iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-11/+11
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-34/+34
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-1/+3
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+1
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-2/+2
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-34/+34
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-4/+4
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-34/+34
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-34/+34
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*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	1	-21/+21
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-2/+2
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-40/+40
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-40/+40
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*	Use log_abort() and log_assert() in BTOR backend	Clifford Wolf	2014-03-07	1	-18/+17
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*	modified btor synthesis script for correct use of splice command.	Ahmed Irfan	2014-02-12	2	-6/+6
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*	disabling splice command in the script	Ahmed Irfan	2014-02-11	2	-2/+6
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*	register output corrected	Ahmed Irfan	2014-02-11	1	-1/+1
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*	added concat and slice cell translation	Ahmed Irfan	2014-02-11	3	-36/+59
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*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06	1	-1/+1
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*	Added BTOR backend README file	Clifford Wolf	2014-02-05	2	-1/+24
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	2	-1/+6
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*	root bug corrected	Ahmed Irfan	2014-01-25	1	-1/+5
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*	removed regex include	Ahmed Irfan	2014-01-24	1	-1/+0
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*	merged clifford changes + removed regex	Ahmed Irfan	2014-01-24	1	-26/+52
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*	Use techmap -share_map in btor scripts	Clifford Wolf	2014-01-24	2	-2/+2
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*	Moved btor scripts to backends/btor/	Clifford Wolf	2014-01-24	2	-0/+50
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*	slice bug corrected	Ahmed Irfan	2014-01-20	1	-1/+1
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*	assert feature	Ahmed Irfan	2014-01-20	1	-9/+40
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*	verilog default options pull	Ahmed Irfan	2014-01-17	1	-28/+97
\| \| \| \|	shift operator width issues
*	slice error corrected	Ahmed Irfan	2014-01-16	1	-5/+5
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*	width issues	Ahmed Irfan	2014-01-15	1	-64/+87
\| \| \| \|	dff cell for more than one registers
*	BTOR backend	Ahmed Irfan	2014-01-14	1	-274/+328
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*	btor	Ahmed Irfan	2014-01-03	2	-0/+774