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Author
Age
Files
Lines
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-3
/
+3
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-2
/
+2
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
1
-34
/
+34
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-4
/
+4
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-34
/
+34
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-34
/
+34
*
Various RTLIL::SigSpec related code cleanups
Clifford Wolf
2014-07-25
1
-21
/
+21
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
1
-2
/
+2
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-40
/
+40
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-40
/
+40
*
Use log_abort() and log_assert() in BTOR backend
Clifford Wolf
2014-03-07
1
-18
/
+17
*
modified btor synthesis script for correct use of splice command.
Ahmed Irfan
2014-02-12
2
-6
/
+6
*
disabling splice command in the script
Ahmed Irfan
2014-02-11
2
-2
/
+6
*
register output corrected
Ahmed Irfan
2014-02-11
1
-1
/
+1
*
added concat and slice cell translation
Ahmed Irfan
2014-02-11
3
-36
/
+59
*
Fixed gcc compiler warnings with release build
Clifford Wolf
2014-02-06
1
-1
/
+1
*
Added BTOR backend README file
Clifford Wolf
2014-02-05
2
-1
/
+24
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
2
-1
/
+6
*
root bug corrected
Ahmed Irfan
2014-01-25
1
-1
/
+5
*
removed regex include
Ahmed Irfan
2014-01-24
1
-1
/
+0
*
merged clifford changes + removed regex
Ahmed Irfan
2014-01-24
1
-26
/
+52
*
Use techmap -share_map in btor scripts
Clifford Wolf
2014-01-24
2
-2
/
+2
*
Moved btor scripts to backends/btor/
Clifford Wolf
2014-01-24
2
-0
/
+50
*
slice bug corrected
Ahmed Irfan
2014-01-20
1
-1
/
+1
*
assert feature
Ahmed Irfan
2014-01-20
1
-9
/
+40
*
verilog default options pull
Ahmed Irfan
2014-01-17
1
-28
/
+97
*
slice error corrected
Ahmed Irfan
2014-01-16
1
-5
/
+5
*
width issues
Ahmed Irfan
2014-01-15
1
-64
/
+87
*
BTOR backend
Ahmed Irfan
2014-01-14
1
-274
/
+328
*
btor
Ahmed Irfan
2014-01-03
2
-0
/
+774