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path: root/backends/btor/verilog2btor.sh
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* Renamed opt_const to opt_exprClifford Wolf2016-03-311-1/+1
* Another block of spelling fixesLarry Doolittle2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-6/+6
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-081-1/+1
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-221-2/+2
* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-121-3/+2
* disabling splice command in the scriptAhmed Irfan2014-02-111-1/+3
* added concat and slice cell translationAhmed Irfan2014-02-111-2/+2
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-1/+2
* Use techmap -share_map in btor scriptsClifford Wolf2014-01-241-1/+1
* Moved btor scripts to backends/btor/Clifford Wolf2014-01-241-0/+35