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* Minor style fixesClifford Wolf2018-12-181-1/+1
* Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-171-2/+38
* Fix btor init value handlingClifford Wolf2018-12-081-9/+13
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Add "no driver for signal bit" error msg to btor back-endClifford Wolf2017-12-241-0/+2
* Simple fix BTOR memory encodingClifford Wolf2017-12-171-2/+2
* Improve BTOR memory encodingClifford Wolf2017-12-171-2/+16
* Add array support to btor back-endClifford Wolf2017-12-151-6/+169
* Add $anyconst/$anyseq support to btor back-endClifford Wolf2017-12-151-13/+51
* Add "write_btor -s" modeClifford Wolf2017-12-131-6/+50
* Add state initval handling to btor back-endClifford Wolf2017-12-121-0/+25
* Add btor back-end support for 'x' constantsClifford Wolf2017-12-121-1/+54
* Add btor $shift/$shiftx supportClifford Wolf2017-12-111-5/+35
* Fix btor back-end shift handlingClifford Wolf2017-12-101-4/+6
* Add support for $pmux in btor back-endClifford Wolf2017-12-101-0/+23
* Add support for more cell types to btor back-endClifford Wolf2017-12-101-6/+215
* Fix btor concatClifford Wolf2017-12-091-1/+1
* Bugfixes in new BTOR back-endClifford Wolf2017-11-241-2/+3
* Progress in new BTOR back-endClifford Wolf2017-11-231-36/+97
* Progress in new BTOR back-endClifford Wolf2017-11-231-3/+95
* Progress in new BTOR back-endClifford Wolf2017-11-231-14/+72
* Progress with new BTOR backendClifford Wolf2017-11-231-8/+109
* Add skeleton for new BTOR back-endClifford Wolf2017-11-231-0/+213
* Remove old BTOR back-endClifford Wolf2017-11-231-1111/+0
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Added "int ceil_log2(int)" functionClifford Wolf2016-02-131-8/+8
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-2/+2
* Remove some very strange whitespace in btor.cc (by Larry Doolittle)Clifford Wolf2015-08-051-7/+7
* Fixed trailing whitespacesClifford Wolf2015-07-021-82/+82
* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-111-1/+1
* separated memory next from write cellAhmed Irfan2015-04-031-7/+55
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-2/+2
* namespace YosysClifford Wolf2014-09-271-0/+4
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-221-197/+197
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| * Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-011-1/+2
| * Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-65/+65
| * No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
| * More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-11/+11
| * Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-34/+34
| * Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-1/+3
| * Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+1
| * Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-2/+2
| * Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
| * Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-2/+2
| * More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-34/+34
| * Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-34/+34
| * Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-34/+34
| * Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-251-21/+21
| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-2/+2
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