iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed cstr_buf for std::string with small string optimization	Clifford Wolf	2015-06-11	1	-1/+1
*	Improvements in BLIF front-end	Clifford Wolf	2015-05-24	1	-0/+1
*	Added write_blif -attr	Clifford Wolf	2015-03-02	1	-18/+33
*	Fixed another bug in write_blif handling of $lut cells	Clifford Wolf	2014-12-19	1	-1/+1
*	Fixed writing of $lut cells in BLIF backend	Clifford Wolf	2014-12-17	1	-7/+7
*	Added "write_blif -undef" and support for special "-" true/false/undef type	Clifford Wolf	2014-12-14	1	-13/+33
*	Added "write_blif -blackbox"	Clifford Wolf	2014-12-14	1	-2/+16
*	Added "blif -unbuf" feature	Clifford Wolf	2014-12-14	1	-0/+19
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-48/+48
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-2/+2
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-1/+1
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-10/+10
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-4/+4
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-12/+12
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-12/+12
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-8/+6
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-12/+12
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-12/+12
*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22	1	-0/+23
*	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21	1	-17/+65
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	1	-0/+5
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
*	Write yosys version to output files	Clifford Wolf	2013-11-03	1	-0/+2
*	Added placeholder check to dfflibmap and cleaned up some other placeholder ch...	Clifford Wolf	2013-10-31	1	-1/+1
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-1/+1
*	Added -buf, -true and -false options to blif backend	Clifford Wolf	2013-10-17	1	-2/+40
*	Improvements in EDIF backend	Clifford Wolf	2013-09-17	1	-1/+1
*	Added additional options to BLIF backend	Clifford Wolf	2013-09-15	1	-15/+60
*	Added BLIF backend	Clifford Wolf	2013-09-15	2	-0/+245