iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-3/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-2/+2
*	Fixed gentb_constant handling in autotest backend	Clifford Wolf	2013-12-04	1	-2/+2
*	Added modelsim support to autotest	Clifford Wolf	2013-11-24	1	-6/+6
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24	1	-1/+6
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-3/+3
*	Added more help messages	Clifford Wolf	2013-03-01	1	-1/+23
*	initial import	Clifford Wolf	2013-01-05	1	-0/+309