iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	codeowners: adopt ABC9 and update intel_alm username	Lofty	2022-06-20	1	-2/+2
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*	Merge pull request #2019 from boqwxp/glift	Claire Xen	2022-02-11	1	-0/+1
\|\ \| \| \| \|	Add `glift` command for creating gate-level information flow tracking models and optimization problems
\| *	glift: Add CODEOWNERS entry.	Alberto Gonzalez	2020-07-01	1	-0/+1
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* \|	Update CHANGELOG and CODEOWNERS	Miodrag Milanovic	2021-12-01	1	-0/+1
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* \|	Update CODEOWNERS	Miodrag Milanović	2021-11-08	1	-0/+1
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* \|	abc9: fix SCC issues (#2694)	Eddie Hung	2021-03-29	1	-0/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep ) on wires abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* \|	CODEOWNERS: add @zachjs as Verilog/AST frontend owner	whitequark	2020-12-27	1	-0/+3
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* \|	qbfsat: Clean up and refactor data structures into `qbfsat.h`.	Alberto Gonzalez	2020-07-01	1	-0/+1
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*	Add codeowners file (#2098)	N. Engelhardt	2020-06-04	1	-0/+37