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| author | whitequark <whitequark@whitequark.org> | 2020-12-27 05:00:04 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-27 05:00:04 +0000 |
| commit | cb2283389df6fbd2f6aa8393e8d1960123ec72f4 (patch) | |
| tree | fb9225125004f77ce5876cbcd3142bb663981b0b /CODEOWNERS | |
| parent | af457ce8d05bb57a48831c3c252c708625ae0ffd (diff) | |
| download | yosys-cb2283389df6fbd2f6aa8393e8d1960123ec72f4.tar.gz yosys-cb2283389df6fbd2f6aa8393e8d1960123ec72f4.tar.bz2 yosys-cb2283389df6fbd2f6aa8393e8d1960123ec72f4.zip | |
CODEOWNERS: add @zachjs as Verilog/AST frontend owner
Diffstat (limited to 'CODEOWNERS')
| -rw-r--r-- | CODEOWNERS | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/CODEOWNERS b/CODEOWNERS index 350a62120..0419e6e44 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -25,6 +25,9 @@ passes/opt/opt_lut.cc @whitequark # These still override previous lines, so be careful not to # accidentally disable any of the above rules. +frontends/verilog/ @zachjs +frontends/ast/ @zachjs + techlibs/intel_alm/ @ZirconiumX # pyosys |