| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| * | | | Merge pull request #2779 from YosysHQ/mwk/nuke-travis | Miodrag Milanović | 2021-05-24 | 5 | -279/+0 | |
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| | * | | | Remove Travis CI. | Marcelina Kościelnicka | 2021-05-24 | 5 | -279/+0 | |
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| * | | | backend/firrtl: Convert to use Mem helpers. | Marcelina Kościelnicka | 2021-05-24 | 1 | -264/+88 | |
| * | | | github actions: Test on several gcc and clang versions on Linux. | Marcelina Kościelnicka | 2021-05-24 | 1 | -6/+31 | |
| * | | | memory_share: Use Mem helpers. | Marcelina Kościelnicka | 2021-05-23 | 1 | -89/+71 | |
| * | | | extract_rdff: Add initvals parameter. | Marcelina Kościelnicka | 2021-05-23 | 4 | -11/+18 | |
| * | | | btor: Use is_mem_cell in one more place. | Marcelina Kościelnicka | 2021-05-23 | 1 | -1/+1 | |
| * | | | memory_share: Split off feedback path finding as a separate pass. | Marcelina Kościelnicka | 2021-05-23 | 4 | -242/+343 | |
| * | | | Add new helper class for merging FFs into cells, use for memory_dff. | Marcelina Kościelnicka | 2021-05-23 | 7 | -240/+596 | |
| * | | | opt_mem: Remove write ports with const-0 EN. | Marcelina Kościelnicka | 2021-05-23 | 2 | -0/+46 | |
| * | | | memory_memx: Use Mem helper. | Marcelina Kościelnicka | 2021-05-22 | 1 | -42/+31 | |
| * | | | kernel/rtlil: Extract some helpers for checking memory cell types. | Marcelina Kościelnicka | 2021-05-22 | 10 | -28/+24 | |
| * | | | kernel/mem: Add a check() function. | Marcelina Kościelnicka | 2021-05-22 | 2 | -0/+26 | |
| * | | | kernel/mem: defer port removal to emit() | Marcelina Kościelnicka | 2021-05-22 | 2 | -18/+38 | |
| * | | | memory_dff: Use Mem helper. | Marcelina Kościelnicka | 2021-05-21 | 1 | -19/+26 | |
| * | | | Run VS build on PRs and each push | Miodrag Milanović | 2021-05-20 | 1 | -4/+1 | |
| * | | | Bump version | Marcelina Kościelnicka | 2021-05-20 | 1 | -1/+1 | |
| * | | | tests/blif: Add missing gitignore | Marcelina Kościelnicka | 2021-05-20 | 1 | -0/+1 | |
| * | | | Visual Studio build action | Miodrag Milanovic | 2021-05-17 | 1 | -0/+40 | |
| * | | | intel_alm: Fix illegal carry chains | gatecat | 2021-05-15 | 4 | -7/+9 | |
| * | | | intel_alm: Add global buffer insertion | gatecat | 2021-05-15 | 19 | -45/+119 | |
| * | | | intel_alm: Add IO buffer insertion | gatecat | 2021-05-15 | 19 | -46/+166 | |
| * | | | Change the type of current_module to Module | Rupert Swarbrick | 2021-05-13 | 2 | -24/+26 | |
| * | | | Use range-based for loop in AST::process | Rupert Swarbrick | 2021-05-13 | 1 | -21/+21 | |
| * | | | Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib. | Adam Greig | 2021-05-12 | 1 | -0/+22 | |
| * | | | sv: check validity of package end label | Zachary Snow | 2021-05-10 | 2 | -0/+17 | |
| * | | | blif: Use library cells' start_offset and upto for wideports. | Marcelina Kościelnicka | 2021-05-08 | 4 | -10/+54 | |
| * | | | connect: Add -assert option, fix non-working sigmap. | Marcelina Kościelnicka | 2021-05-08 | 1 | -4/+24 | |
| * | | | opt_dff: Fix NOT gates wired in reverse. | Marcelina Kościelnicka | 2021-05-04 | 2 | -10/+15 | |
| * | | | Merge pull request #2738 from mdko/xilinx-blif | Miodrag Milanović | 2021-04-27 | 1 | -1/+1 | |
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| | * | | | Fix use of blif name in synth_xilinx command | Michael Christensen | 2021-04-27 | 1 | -1/+1 | |
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| * | | | Merge pull request #2737 from YosysHQ/claire/fix2736 | Claire Xen | 2021-04-26 | 1 | -0/+4 | |
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| | * | | | Remove duplicates from conns array in JSON front-end, fixes #2736 | Claire Xenia Wolf | 2021-04-26 | 1 | -0/+4 | |
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| * | | | Merge pull request #2669 from YosysHQ/claire/ice40defaults | Claire Xen | 2021-04-21 | 2 | -26/+62 | |
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| | * | | | Add default assignments to other SB_* simulation models | Claire Xenia Wolf | 2021-04-20 | 1 | -24/+44 | |
| | * | | | Add default assignments to SB_LUT4 | Claire Xenia Wolf | 2021-04-20 | 2 | -2/+18 | |
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| * | | | quicklogic: ABC9 synthesis | Lofty | 2021-04-17 | 12 | -22/+97 | |
| * | | | sf2: fix name of AND modules | Stefan Riesenberger | 2021-04-09 | 1 | -3/+3 | |
| * | | | Merge pull request #2724 from whitequark/flatten-rewrite-memwr-memid | whitequark | 2021-04-09 | 1 | -0/+3 | |
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| | * | | | flatten: rewrite memid in memwr actions. | whitequark | 2021-04-09 | 1 | -0/+3 | |
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| * | | | preproc: test coverage for #2712 | Zachary Snow | 2021-03-30 | 3 | -0/+18 | |
| * | | | equiv: Suggest running async2sync or clk2fflogic where appropriate. | Marcelina Kościelnicka | 2021-03-30 | 2 | -3/+10 | |
| * | | | verilog: revise hot comment warnings | Zachary Snow | 2021-03-30 | 1 | -6/+21 | |
| * | | | abc9: uniquify blackboxes like whiteboxes (#2695) | Eddie Hung | 2021-03-29 | 2 | -11/+62 | |
| * | | | abc9: fix SCC issues (#2694) | Eddie Hung | 2021-03-29 | 9 | -45/+94 | |
| * | | | Bump version | Marcelina Kościelnicka | 2021-03-30 | 1 | -1/+1 | |
| * | | | preproc: Fix up conditional handling. | Marcelina Kościelnicka | 2021-03-30 | 1 | -3/+17 | |
| * | | | gha: trim macOS dependencies | Zachary Snow | 2021-03-28 | 1 | -3/+1 | |
| * | | | gha: combine jobs using matrix | Zachary Snow | 2021-03-28 | 1 | -43/+24 | |
| * | | | rtlil: add const accessors for modules, wires, and cells | Zachary Snow | 2021-03-25 | 2 | -0/+15 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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