aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* | | Merge pull request #2779 from YosysHQ/mwk/nuke-travisMiodrag Milanović2021-05-245-279/+0
|\ \ \
| * | | Remove Travis CI.Marcelina Kościelnicka2021-05-245-279/+0
|/ / /
* | | backend/firrtl: Convert to use Mem helpers.Marcelina Kościelnicka2021-05-241-264/+88
* | | github actions: Test on several gcc and clang versions on Linux.Marcelina Kościelnicka2021-05-241-6/+31
* | | memory_share: Use Mem helpers.Marcelina Kościelnicka2021-05-231-89/+71
* | | extract_rdff: Add initvals parameter.Marcelina Kościelnicka2021-05-234-11/+18
* | | btor: Use is_mem_cell in one more place.Marcelina Kościelnicka2021-05-231-1/+1
* | | memory_share: Split off feedback path finding as a separate pass.Marcelina Kościelnicka2021-05-234-242/+343
* | | Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-237-240/+596
* | | opt_mem: Remove write ports with const-0 EN.Marcelina Kościelnicka2021-05-232-0/+46
* | | memory_memx: Use Mem helper.Marcelina Kościelnicka2021-05-221-42/+31
* | | kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-2210-28/+24
* | | kernel/mem: Add a check() function.Marcelina Kościelnicka2021-05-222-0/+26
* | | kernel/mem: defer port removal to emit()Marcelina Kościelnicka2021-05-222-18/+38
* | | memory_dff: Use Mem helper.Marcelina Kościelnicka2021-05-211-19/+26
* | | Run VS build on PRs and each pushMiodrag Milanović2021-05-201-4/+1
* | | Bump versionMarcelina Kościelnicka2021-05-201-1/+1
* | | tests/blif: Add missing gitignoreMarcelina Kościelnicka2021-05-201-0/+1
* | | Visual Studio build actionMiodrag Milanovic2021-05-171-0/+40
* | | intel_alm: Fix illegal carry chainsgatecat2021-05-154-7/+9
* | | intel_alm: Add global buffer insertiongatecat2021-05-1519-45/+119
* | | intel_alm: Add IO buffer insertiongatecat2021-05-1519-46/+166
* | | Change the type of current_module to ModuleRupert Swarbrick2021-05-132-24/+26
* | | Use range-based for loop in AST::processRupert Swarbrick2021-05-131-21/+21
* | | Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.Adam Greig2021-05-121-0/+22
* | | sv: check validity of package end labelZachary Snow2021-05-102-0/+17
* | | blif: Use library cells' start_offset and upto for wideports.Marcelina Kościelnicka2021-05-084-10/+54
* | | connect: Add -assert option, fix non-working sigmap.Marcelina Kościelnicka2021-05-081-4/+24
* | | opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-042-10/+15
* | | Merge pull request #2738 from mdko/xilinx-blifMiodrag Milanović2021-04-271-1/+1
|\ \ \
| * | | Fix use of blif name in synth_xilinx commandMichael Christensen2021-04-271-1/+1
|/ / /
* | | Merge pull request #2737 from YosysHQ/claire/fix2736Claire Xen2021-04-261-0/+4
|\ \ \
| * | | Remove duplicates from conns array in JSON front-end, fixes #2736Claire Xenia Wolf2021-04-261-0/+4
|/ / /
* | | Merge pull request #2669 from YosysHQ/claire/ice40defaultsClaire Xen2021-04-212-26/+62
|\ \ \
| * | | Add default assignments to other SB_* simulation modelsClaire Xenia Wolf2021-04-201-24/+44
| * | | Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-202-2/+18
|/ / /
* | | quicklogic: ABC9 synthesisLofty2021-04-1712-22/+97
* | | sf2: fix name of AND modulesStefan Riesenberger2021-04-091-3/+3
* | | Merge pull request #2724 from whitequark/flatten-rewrite-memwr-memidwhitequark2021-04-091-0/+3
|\ \ \
| * | | flatten: rewrite memid in memwr actions.whitequark2021-04-091-0/+3
|/ / /
* | | preproc: test coverage for #2712Zachary Snow2021-03-303-0/+18
* | | equiv: Suggest running async2sync or clk2fflogic where appropriate.Marcelina Kościelnicka2021-03-302-3/+10
* | | verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
* | | abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-292-11/+62
* | | abc9: fix SCC issues (#2694)Eddie Hung2021-03-299-45/+94
* | | Bump versionMarcelina Kościelnicka2021-03-301-1/+1
* | | preproc: Fix up conditional handling.Marcelina Kościelnicka2021-03-301-3/+17
* | | gha: trim macOS dependenciesZachary Snow2021-03-281-3/+1
* | | gha: combine jobs using matrixZachary Snow2021-03-281-43/+24
* | | rtlil: add const accessors for modules, wires, and cellsZachary Snow2021-03-252-0/+15