iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Disabled RTLIL::SigSpec::check() in release builds	Clifford Wolf	2014-07-23	1	-0/+2
*	Fixed release build	Clifford Wolf	2014-07-23	1	-0/+2
*	Various fixes in Verific frontend for new RTLIL API	Clifford Wolf	2014-07-23	2	-27/+55
*	Added RTLIL::SigSpec::repeat()	Clifford Wolf	2014-07-23	2	-0/+10
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23	2	-5/+5
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	24	-181/+15
*	Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ...	Clifford Wolf	2014-07-23	1	-7/+42
*	Fixed manual/CHAPTER_Prog/stubnets.cc	Clifford Wolf	2014-07-23	1	-2/+2
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	16	-429/+231
*	Added eclipse .setting folder to .gitignore	Clifford Wolf	2014-07-23	1	-0/+1
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	11	-88/+77
*	Replaced RTLIL::SigSpec::operator!=() with inline version	Clifford Wolf	2014-07-23	2	-8/+1
*	Merge branch: Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor	Clifford Wolf	2014-07-23	16	-39/+55
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\| *	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	16	-51/+43
\| *	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	15	-47/+33
\| *	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	Clifford Wolf	2014-07-23	4	-7/+45
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*	Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)	Clifford Wolf	2014-07-23	2	-6/+6
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22	3	-58/+56
*	SigSpec refactoring: Added RTLIL::SigSpecIterator	Clifford Wolf	2014-07-22	1	-6/+28
*	SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands	Clifford Wolf	2014-07-22	3	-38/+19
*	Fixed memory corruption with new SigSpec API in proc_mux	Clifford Wolf	2014-07-22	1	-7/+3
*	SigSpec refactoring: added RTLIL::SigSpec::operator[]	Clifford Wolf	2014-07-22	1	-1/+4
*	fixed memory leak in fsm_opt	Clifford Wolf	2014-07-22	1	-1/+3
*	SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form	Clifford Wolf	2014-07-22	1	-182/+113
*	Removed RTLIL::SigChunk::compare()	Clifford Wolf	2014-07-22	2	-25/+5
*	SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api	Clifford Wolf	2014-07-22	2	-18/+135
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	20	-34/+29
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22	3	-94/+18
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	62	-800/+800
*	SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad...	Clifford Wolf	2014-07-22	2	-152/+158
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	62	-951/+954
*	Fixed ilang parsing of process attributes	Clifford Wolf	2014-07-22	1	-0/+1
*	Fixed make rules for ilang parser	Clifford Wolf	2014-07-22	1	-1/+3
*	Use "opt -fine" in test/vloght/test_mapopt.sh	Clifford Wolf	2014-07-21	2	-2/+3
*	Added "opt_const -keepdc"	Clifford Wolf	2014-07-21	2	-15/+168
*	Added mul to mux conversion to "opt_const -fine"	Clifford Wolf	2014-07-21	1	-0/+55
*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21	4	-16/+145
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21	3	-26/+24
*	Added opt_const support for simple identities	Clifford Wolf	2014-07-21	1	-0/+69
*	Various improvements in test/vloghtb	Clifford Wolf	2014-07-21	4	-30/+52
*	Added support for scripts with labels	Clifford Wolf	2014-07-21	1	-11/+74
*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21	4	-25/+22
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	11	-56/+47
*	Wider range of cell types supported in "share" pass	Clifford Wolf	2014-07-21	3	-36/+249
*	Bugfix in satgen for cells with wider in- than outputs.	Clifford Wolf	2014-07-21	1	-1/+9
*	Added module->remove(), module->addWire(), module->addCell(), cell->check()	Clifford Wolf	2014-07-21	2	-8/+44
*	Added log_ping()	Clifford Wolf	2014-07-21	1	-0/+1
*	Use ezSAT::non_incremental() in "share" pass	Clifford Wolf	2014-07-21	1	-0/+2
*	Added ezSAT::keep_cnf() and ezSAT::non_incremental()	Clifford Wolf	2014-07-21	5	-8/+71
*	Fixed ezSAT stand-alone build	Clifford Wolf	2014-07-21	2	-8/+4