iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
*	- frontends/vhdl2verilog/vhdl2verilog.cc: #include <cerrno> for errno; use ↵	Siesh1oo	2014-03-10	1	-4/+11
\| \| \| \|	POSIX getcwd() for portability.
*	- kernel/register.cc: need to #include <cerrno> or errno.h for errno.	Siesh1oo	2014-03-10	1	-0/+1
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*	- kernel/driver.cc: need to #include <cerrno> or errno.h for errno.	Siesh1oo	2014-03-10	1	-0/+1
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*	- kernel/log.h: add rusage()-based fallback for systems without ↵	Siesh1oo	2014-03-10	1	-0/+16
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*	- libs/ezsat/ezsat.cc: need to #include <cmath> or math.h for math functions.	Siesh1oo	2014-03-10	1	-1/+2
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*	- passes/abc/abc.cc: #include <cerrno> for errno; use POSIX getcwd() for ↵	Siesh1oo	2014-03-10	1	-2/+6
\| \| \| \|	portability (get_current_dir_name() does not exist on BSD).
*	- passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode.cc, ↵	Siesh1oo	2014-03-10	3	-1/+4
\| \| \| \|	passes/cmds/select.cc: #include <cerrno> for errno, use c++-style includes.
*	Fixed a typo in RTLIL::Module::addReduce...	Clifford Wolf	2014-03-10	1	-5/+5
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*	Improved verific command (added support for some operators)	Clifford Wolf	2014-03-10	1	-2/+160
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*	Improvements in verific command	Clifford Wolf	2014-03-10	1	-59/+39
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*	Added RTLIL::Module::add... helper methods	Clifford Wolf	2014-03-10	2	-0/+293
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*	Added "verific" command	Clifford Wolf	2014-03-09	3	-2/+501
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*	Fixed dumping of timing() { .. } block in libparse	Clifford Wolf	2014-03-09	1	-2/+3
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*	Verbose reading of liberty and constr files in ABC pass	Clifford Wolf	2014-03-09	1	-2/+2
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*	Fixed bug in freduce command	Clifford Wolf	2014-03-07	1	-0/+30
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*	Some minor code cleanups in freduce command	Clifford Wolf	2014-03-07	1	-5/+5
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*	Bugfix in ilang frontend autoidx recovery	Clifford Wolf	2014-03-07	1	-2/+2
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*	Use log_abort() and log_assert() in BTOR backend	Clifford Wolf	2014-03-07	1	-18/+17
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*	Added freduce -dump	Clifford Wolf	2014-03-06	1	-1/+24
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*	Added freduce -stop	Clifford Wolf	2014-03-06	1	-3/+18
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*	Fixed gcc compiler warning	Clifford Wolf	2014-03-06	1	-1/+2
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*	Fixed undef handling in opt_reduce	Clifford Wolf	2014-03-06	1	-2/+2
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*	Fixes for improved techmap of shifts with large B inputs	Clifford Wolf	2014-03-06	1	-8/+8
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*	Fixed use of frozen literals in SatGen	Clifford Wolf	2014-03-06	1	-3/+2
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*	Strictly zero-extend unsigned A-inputs of shift operations in techmap	Clifford Wolf	2014-03-06	1	-4/+4
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*	Added techmap -max_iter option	Clifford Wolf	2014-03-06	1	-0/+10
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*	Improved techmap of shift with wide B inputs	Clifford Wolf	2014-03-06	1	-13/+37
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*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06	2	-3/+3
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*	Switched to EZMINISAT_SIMPSOLVER as default SAT solver	Clifford Wolf	2014-03-05	1	-1/+1
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*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05	1	-0/+6
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*	Fixed merging of compatible wire decls in AST frontend	Clifford Wolf	2014-03-05	1	-1/+4
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*	Bugfix in recursive AST simplification	Clifford Wolf	2014-03-05	1	-10/+22
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*	fixed freduce for Minisat::SimpSolver: use frozen_literal()	Clifford Wolf	2014-03-03	1	-2/+2
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*	ezSAT: Added frozen_literal() API	Clifford Wolf	2014-03-03	2	-0/+16
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*	ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressions	Clifford Wolf	2014-03-03	2	-8/+23
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*	Added ezSAT::eliminated API to help the SAT solver remember eliminated variables	Clifford Wolf	2014-03-01	4	-3/+17
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*	ezSAT bugfix: don't call virtual methods in base class constructor	Clifford Wolf	2014-03-01	2	-2/+5
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*	Removed ezSAT::assumed() API	Clifford Wolf	2014-03-01	3	-10/+0
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*	Removed ezSAT built-in brute-froce solver	Clifford Wolf	2014-03-01	1	-102/+6
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*	Fixed vhdl2verilog temp dir name	Clifford Wolf	2014-03-01	1	-1/+1
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*	Fixed vhdl2verilog help message	Clifford Wolf	2014-03-01	1	-3/+2
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*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27	2	-1/+2
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*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26	1	-5/+5
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*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26	1	-4/+4
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*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24	1	-1/+1
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*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23	5	-11/+79
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*	Fixed small memory leak in Pass::call()	Clifford Wolf	2014-02-23	1	-1/+4
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*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22	1	-4/+6
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*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22	1	-1/+1
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*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22	1	-0/+23
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