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* fabulous: improvements to the passgatecat2022-11-1713-139/+340
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Unify and update primitivesgatecat2022-11-173-852/+356
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Introduce RegFile mappingsTaoBi222022-11-174-2/+95
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* Replace synth call with components, reintroduce flags and correct vpr flag ↵TaoBi222022-11-171-4/+76
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* Reorder operations to load in primitive library before hierarchy passTaoBi222022-11-171-5/+6
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* Add plib flag to specify custom primitive library pathTaoBi222022-11-171-2/+14
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* Remove flattening from FABulous passTaoBi222022-11-171-11/+2
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* Remove ALL currently unused flags (some to be reintroduced later and passed ↵TaoBi222022-11-171-82/+3
| | | | through to synth)
* Add synth_fabulous ScriptPassTaoBi222022-11-178-0/+1282
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* Bump versiongithub-actions[bot]2022-11-171-1/+1
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* Slowing down clock to have same metadataMiodrag Milanovic2022-11-161-2/+2
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* Bump versiongithub-actions[bot]2022-11-161-1/+1
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* faketime to make PDFs uniqueMiodrag Milanovic2022-11-151-2/+2
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* Rst docs conversion (#3496)KrystalDelusion2022-11-1557-2/+7792
| | | Rst docs conversion
* Merge pull request #3547 from YosysHQ/update_abcMiodrag Milanović2022-11-141-1/+1
|\ | | | | Update ABC
| * Update ABCMiodrag Milanovic2022-11-091-1/+1
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* | Bump versiongithub-actions[bot]2022-11-101-1/+1
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* | Add missing memory width assert preventing division by zero (#3546)Emil J2022-11-091-0/+1
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* Bump versiongithub-actions[bot]2022-11-091-1/+1
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* Next dev cycleMiodrag Milanovic2022-11-082-2/+5
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* Release version 0.23Miodrag Milanovic2022-11-082-3/+3
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* Update manualMiodrag Milanovic2022-11-081-0/+47
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* Bump versiongithub-actions[bot]2022-11-081-1/+1
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* Merge pull request #3544 from jix/cosim-ffinitJannis Harder2022-11-071-12/+11
|\ | | | | sim: Run a comb-only update step to set past values during FST cosim
| * sim: Run a comb-only update step to set past values during FST cosimJannis Harder2022-11-071-12/+11
|/ | | | | | | | The previous approach only initialized past_d and past_ad while for FST cosim we also need to initialize the other past values like past_clk, etc. Also to properly initialize them, we need to run a combinational update step in case any of the wires feeding into the FF are private or otherwise not part of the FST.
* Update CHANGELOGMiodrag Milanovic2022-11-071-1/+5
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* Merge pull request #3536 from YosysHQ/claire/vcdendMiodrag Milanović2022-11-071-0/+1
|\ | | | | Add extra time at the end of a sat VCD trace
| * Add extra time at the end of a sat VCD traceClaire Xenia Wolf2022-11-011-0/+1
| | | | | | | | | | | | | | Otherwise the final values will not show up in gtkwave waveforms when looking at the generated traces. Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Merge pull request #3543 from jix/fstdata-fixesMiodrag Milanović2022-11-071-8/+20
|\ \ | | | | | | fstdata: Fixes and improvements
| * | fstdata: Update past_data before end_time callbackJannis Harder2022-11-071-0/+1
| | | | | | | | | | | | Required to make the '-at' parameter work.
| * | fstdata: Handle square/angle bracket replacemnt, change memory handlingJannis Harder2022-11-071-8/+19
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing VCDs smtbmc replaces square brackets with angle brackets to avoid the issues with VCD readers misinterpreting such signal names. For memory addresses it also uses angle brackets and hexadecimal addresses, while other tools will use square brackets and decimal addresses. Previously the code handled both forms of memory addresses, assuming that any signal that looks like a memory address is a memory address. This is not the case when the user uses regular signals whose names include square brackets _or_ when the verific frontend generates such names to represent various constructs. With this change all angular brackets are turned into square brackets when reading the trace _and_ when performing a signal lookup. This means no matter which kind of brackets are used in the design or in the VCD signals will be matched. This will not handle multiple signals that are the same apart from replacing square/angle brackets, but this will cause issues during the VCD writing of smtbmc already. It still uses the distinction between square and angle brackets for memories to decide whether the address is hex or decimal, but even if something looks like a memory and is added to the `memory_to_handle` data, the plain signal added to `name_to_handle` is used as-is, without rewriting the address. This last change is needed to successfully match verific generated signal names that look like memory addresses while keeping memories working at the same time. It may cause regressions when VCD generation was done with a design that had memories but simulation is done with a design where the memories were mapped to registers. This seems like an unusual setup, but could be worked around with some further changes should this be required.
* | Update CHANGELOGMiodrag Milanovic2022-11-071-0/+11
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* | Bump versiongithub-actions[bot]2022-11-051-1/+1
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* | Separate deprecated compilers on CIMiodrag Milanovic2022-11-042-14/+21
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* Bump versiongithub-actions[bot]2022-11-011-1/+1
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* Merge pull request #3533 from YosysHQ/micko/libertyMiodrag Milanović2022-10-312-1/+84
|\ | | | | Liberty file support using verific library
| * Add additional help infoMiodrag Milanovic2022-10-311-0/+2
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| * Enable importing blackbox modules onlyMiodrag Milanovic2022-10-311-1/+33
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| * Support for reading liberty files using verificMiodrag Milanovic2022-10-312-1/+50
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* | Merge pull request #3534 from mmicko/win32_pluginsMiodrag Milanović2022-10-313-6/+942
|\ \ | |/ |/| Plugin support for mingw windows builds
| * Windows plugin build supportMiodrag Milanovic2022-10-311-6/+28
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| * Add dlfcn library for win32Miodrag Milanovic2022-10-282-0/+914
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* | Bump versiongithub-actions[bot]2022-10-311-1/+1
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* | Add missing log_dump_val_worker forward declarationsClaire Xenia Wolf2022-10-301-0/+5
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Bump versiongithub-actions[bot]2022-10-301-1/+1
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* | Merge pull request #3530 from jix/simlib-mux-fixJannis Harder2022-10-291-4/+2
|\ \ | |/ |/| simlib: Simplify recently changed $mux model
| * simlib: Simplify recently changed $mux modelJannis Harder2022-10-281-4/+2
|/ | | | | | The use of a procedural continuous assignment introduced in #3526 was unintended and is completely unnecessary for the actual change of that PR.
* Bump versiongithub-actions[bot]2022-10-251-1/+1
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* Merge pull request #3528 from YosysHQ/claire/crossbitsClaire Xen2022-10-251-4/+32
|\ | | | | Add miter -cross option
| * Add miter -cross optionClaire Xenia Wolf2022-10-241-4/+32
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