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* opt_expr: optimise 1-bit $xor or $_XOR_ with constant inputEddie Hung2020-03-191-1/+14
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* Added filter-out for libyosys.soMiodrag Milanovic2020-03-121-1/+1
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* Revert "Clean up 'install' Makefile target"Miodrag Milanovic2020-03-121-4/+7
| | | | This reverts commit 2a746234fec2f6d14e9bfa40fd7f3478cdd539ea.
* Revert "Improve ABC repository management in Makefile"Miodrag Milanovic2020-03-121-5/+1
| | | | This reverts commit 90404e1969443a1b8a767ab8f3dc311709c5fe9d.
* Merge pull request #1666 from Xiretza/improve-makefileMiodrag Milanović2020-03-121-8/+9
|\ | | | | Makefile improvements for packaging scripts
| * Improve ABC repository management in MakefileXiretza2020-01-291-1/+5
| | | | | | | | | | | | | | | | | | | | `rev-parse --short` output may have a different abbreviated hash length than ABCREV, so a simple string comparison always fails, even if the correct commit is checked out. Pass both commits through rev-parse and then compare the full hashes instead. Add an `echo-abc-rev` target so that packaging scripts can set ABCPULL=0 and handle all the git nastiness themselves.
| * Clean up 'install' Makefile targetXiretza2020-01-291-7/+4
| | | | | | | | | | | | - libyosys.so is now only installed to LIBDIR instead of LIBDIR, BINDIR and PYTHON_DESTDIR - replace mkdir/cp for single files with `install`
* | Merge pull request #1751 from boqwxp/add_assertN. Engelhardt2020-03-121-1/+57
|\ \ | | | | | | Extend `add` command to allow adding $assert cells.
| * | Extend `add` command to allow adding cells for verification like $assert, ↵Alberto Gonzalez2020-03-101-1/+57
| | | | | | | | | | | | $assume, etc.
* | | Add mandatory wasm file to zip file as wellMiodrag Milanovic2020-03-122-2/+3
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* | | Merge pull request #1757 from jiegec/fix-emccMiodrag Milanović2020-03-124-3/+9
|\ \ \ | | | | | | | | Fix compilation for emcc
| * | | Add EXTRA_EXPORTED_RUNTIME_METHODS env for yosysjsjiegec2020-03-111-0/+1
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| * | | Fix compilation for emccjiegec2020-03-114-3/+8
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* | | Merge pull request #1743 from YosysHQ/eddie/abc9_keepEddie Hung2020-03-113-25/+21
|\ \ \ | | | | | | | | abc9: improve (* keep *) handling
| * | | xaiger: remove some unnecessary operations ...Eddie Hung2020-03-061-9/+2
| | | | | | | | | | | | | | | | | | | | ... since they can not be triggered by (* keep *) anymore (but could still be triggered by (* abc9_scc *) !?!)
| * | | abc9: for sccs, create a new wire instead of using entirety of existingEddie Hung2020-03-061-7/+7
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| * | | abc9: (* keep *) wires to be PO only, not PI as well; fix scc handlingEddie Hung2020-03-062-11/+9
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| * | | abc: add abc.debug scratchpad optionEddie Hung2020-03-061-0/+5
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* | | | Merge pull request #1744 from YosysHQ/eddie/fix1675Eddie Hung2020-03-111-1/+1
|\ \ \ \ | | | | | | | | | | Bump ABCREV to receive fix for #1675
| * | | | Bump ABCREV to receive fix for #1675Eddie Hung2020-03-061-1/+1
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* | | | | Merge pull request #1753 from YosysHQ/dave/abc9-speedupDavid Shah2020-03-103-7/+20
|\ \ \ \ \ | | | | | | | | | | | | Add ScriptPass::run_nocheck and use for abc9
| * | | | | Add ScriptPass::run_nocheck and use for abc9David Shah2020-03-093-7/+20
| | |_|/ / | |/| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #1721 from YosysHQ/dave/tribuf-unusedDavid Shah2020-03-102-2/+15
|\ \ \ \ \ | | | | | | | | | | | | deminout: Don't demote inouts with unused bits
| * | | | | deminout: Don't demote inouts with unused bitsDavid Shah2020-03-042-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | Merge pull request #1755 from boqwxp/add_cmd_cleanupN. Engelhardt2020-03-101-20/+17
|\ \ \ \ \ \ | | | | | | | | | | | | | | Clean up `passes/cmds/add.cc` code style.
| * | | | | | Clean up passes/cmds/add.cc code style.Alberto Gonzalez2020-03-101-20/+17
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* | | | | | Merge pull request #1747 from YosysHQ/claire/partselfixEddie Hung2020-03-092-4/+10
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | Fix partsel expr bit width handling and add test case
| * | | | | Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-082-4/+10
| | |/ / / | |/| | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | | Merge pull request #1716 from zeldin/ecp5_fixN. Engelhardt2020-03-091-2/+0
|\ \ \ \ \ | |/ / / / |/| | | | ecp5: remove unused parameter from \$__ECP5_PDPW16KD
| * | | | remove unused parametersN. Engelhardt2020-03-061-3/+0
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| * | | | ecp5: Add missing parameter to \$__ECP5_PDPW16KDMarcus Comstedt2020-02-221-0/+1
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* | | | | Merge pull request #1742 from nakengelhardt/rpc-test-againMiodrag Milanović2020-03-061-1/+2
|\ \ \ \ \ | |_|_|/ / |/| | | | More rpc test fixes
| * | | | rpc test: make frontend listen before launching yosys & introduce safeguard ↵N. Engelhardt2020-03-061-1/+2
|/ / / / | | | | | | | | | | | | if yosys errors
* | | | Merge pull request #1739 from YosysHQ/eddie/issue1738Eddie Hung2020-03-052-7/+18
|\ \ \ \ | | | | | | | | | | ice40: fix specify for -device {lp,u}
| * | | | ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
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| * | | | tests: extend tests/arch/run-tests.sh for definesEddie Hung2020-03-051-3/+14
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* | | | ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
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* | | | Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1Eddie Hung2020-03-044-109/+244
|\ \ \ \ | | | | | | | | | | xilinx: cleanup DSP48E1 handling for abc9
| * | | | xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
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| * | | | xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
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| * | | | xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
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| * | | | xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
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* | | | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-032-6/+39
|\ \ \ \ \ | | | | | | | | | | | | Add -flowmap option to `synth{,_ice40}`
| * | | | | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-282-6/+39
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* | | | | | Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | | | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-0311-305/+388
|\ \ \ \ \ \ | | | | | | | | | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | | | | | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | line number.
| * | | | | | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | line number.
| * | | | | | Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-239-301/+384
| | |_|_|/ / | |/| | | | | | | | | | | | | | | | and RTLIL nodes.
* | | | | | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
|\ \ \ \ \ \ | | | | | | | | | | | | | | verilog: instead of modifying localparam size, extend init constant expr
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