iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	5	-10/+12
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*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29	1	-1/+1
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*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29	1	-5/+6
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*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29	1	-1/+3
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	4	-10/+29
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	12	-40/+214
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*	Removed left over debug code	Clifford Wolf	2014-07-28	2	-2/+0
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*	Fixed part selects of parameters	Clifford Wolf	2014-07-28	2	-7/+31
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*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28	1	-5/+31
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*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28	1	-2/+2
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*	Fixed width detection for part selects	Clifford Wolf	2014-07-28	1	-2/+2
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*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	6	-22/+96
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	6	-2/+13
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	52	-251/+236
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*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	2	-0/+15
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*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28	1	-0/+22
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*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28	1	-0/+1
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*	Improvements in tests/vloghtb	Clifford Wolf	2014-07-28	2	-11/+17
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*	Added techmap -extern	Clifford Wolf	2014-07-27	3	-17/+92
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*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	3	-4/+43
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	2	-21/+54
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*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	2	-2/+7
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*	Small improvements in PerformanceTimer API	Clifford Wolf	2014-07-27	1	-6/+7
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*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27	1	-1/+1
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*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27	2	-29/+157
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*	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	Clifford Wolf	2014-07-27	1	-9/+26
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*	Added RTLIL::SigSpecConstIterator	Clifford Wolf	2014-07-27	1	-0/+18
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*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27	2	-13/+14
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*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27	4	-8/+7
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*	Fixed verific bindings for new RTLIL api	Clifford Wolf	2014-07-27	2	-55/+42
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*	Fixed ilang parser for new RTLIL API	Clifford Wolf	2014-07-27	1	-10/+10
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	10	-87/+85
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*	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27	2	-2/+20
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*	Added RTLIL::Design::modules()	Clifford Wolf	2014-07-27	1	-0/+3
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	73	-223/+223
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*	Added conversion from ObjRange to std::vector and std::set	Clifford Wolf	2014-07-27	1	-0/+15
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*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27	2	-7/+111
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*	Using std::move() in SigSpec move constructor	Clifford Wolf	2014-07-27	1	-4/+4
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*	Added RTLIL::SigSpec move constructor and move assignment operator	Clifford Wolf	2014-07-27	1	-0/+15
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*	Mostly cosmetic changes to rtlil.h	Clifford Wolf	2014-07-27	1	-17/+57
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	61	-152/+152
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	50	-191/+191
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*	New message for completion of build	Clifford Wolf	2014-07-26	1	-1/+1
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	8	-81/+52
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	19	-218/+150
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*	Added tests/various/.gitignore	Clifford Wolf	2014-07-26	1	-0/+1
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*	Added tests/various/submod_extract.ys	Clifford Wolf	2014-07-26	3	-0/+28
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*	Added support for here documents	Clifford Wolf	2014-07-26	3	-18/+63
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	5	-39/+39
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	12	-27/+33
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