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| * | | | ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-053-2/+11
* | | | | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-2926-40/+540
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| * | | | | Document division and modulo cellsXiretza2020-05-281-0/+23
| * | | | | Update CHANGELOGXiretza2020-05-281-0/+1
| * | | | | Add comments for mod/div semantics to rtlil.hXiretza2020-05-281-0/+4
| * | | | | Expand tests/simple/constmuldivmod.vXiretza2020-05-281-1/+41
| * | | | | Add flooring division operatorXiretza2020-05-2819-24/+213
| * | | | | Add flooring modulo operatorXiretza2020-05-2823-37/+280
* | | | | | Merge pull request #2092 from whitequark/rtlil-no-space-controlclairexen2020-05-292-6/+11
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| * | | | | | Restrict RTLIL::IdString to not contain whitespace or control chars.whitequark2020-05-292-6/+11
* | | | | | | Merge pull request #2017 from boqwxp/qbfsat-cvc4clairexen2020-05-291-2/+6
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| * | | | | | qbfsat: Add support for CVC4.Alberto Gonzalez2020-05-251-2/+6
* | | | | | | Merge pull request #2016 from boqwxp/qbfsat-yicesclairexen2020-05-292-21/+52
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| * | | | | | qbfsat: Move SMT2 info statements back to the top of the file.Alberto Gonzalez2020-05-251-3/+3
| * | | | | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices th...Alberto Gonzalez2020-05-252-23/+54
* | | | | | | Merge pull request #2097 from whitequark/ilang_lexer-fix-erangewhitequark2020-05-291-1/+3
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| * | | | | | | ilang_lexer: fix check for out of range literal.whitequark2020-05-291-1/+3
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* | | | | | | Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
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| * | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRON...Alberto Gonzalez2020-05-061-6/+5
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* | | | | | Merge pull request #2095 from rswarbrick/hier-typowhitequark2020-05-281-2/+2
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| * | | | | | Fix small typos in documentation for hierarchy commandRupert Swarbrick2020-05-281-2/+2
* | | | | | | Merge pull request #2091 from boqwxp/printattrswhitequark2020-05-283-0/+105
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| * | | | | | printattrs: Simplify `get_indent_str()`.Alberto Gonzalez2020-05-281-3/+1
| * | | | | | printattrs: Refactor indentation string building for clarity.Alberto Gonzalez2020-05-271-5/+11
| * | | | | | printattrs: Add test.Alberto Gonzalez2020-05-271-0/+14
| * | | | | | printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.Alberto Gonzalez2020-05-271-8/+15
| * | | | | | misc: Add `printattrs` command.Alberto Gonzalez2020-05-272-0/+80
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* | | | | | Merge pull request #2051 from Xiretza/makefile-cd-warningwhitequark2020-05-281-1/+1
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| * | | | | | Suppress warning during initial clone of ABC repoXiretza2020-05-141-1/+1
* | | | | | | Merge pull request #2031 from epfl-vlsc/masterwhitequark2020-05-281-1/+40
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| * | | | | | | Formatting fixesSahand Kashani2020-05-061-14/+7
| * | | | | | | Add extmodule support to firrtl backendSahand Kashani2020-05-061-1/+47
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* | | | | | | Merge pull request #2063 from boqwxp/techmapped-firrtlwhitequark2020-05-281-10/+12
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| * | | | | | | firrtl: Accept techmapped cell types in FIRRTL backend.Alberto Gonzalez2020-05-171-10/+12
* | | | | | | | Merge pull request #2088 from rswarbrick/count-atwhitequark2020-05-281-2/+8
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| * | | | | | | | Minor optimisation in Module::wire() and Module::cell()Rupert Swarbrick2020-05-261-2/+8
* | | | | | | | | Merge pull request #2087 from rswarbrick/lex-warnwhitequark2020-05-281-1/+3
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| * | | | | | | | | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
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* | | | | | | | | Merge pull request #2086 from rswarbrick/sigbitwhitequark2020-05-281-2/+1
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| * | | | | | | | | Use default copy constructor for RTLIL::SigBitRupert Swarbrick2020-05-261-2/+1
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* | | | | | | | | Merge pull request #2084 from rswarbrick/c_strwhitequark2020-05-281-2/+2
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| * | | | | | | | Use c_str(), not str() for IdString/std::string == and != operatorsRupert Swarbrick2020-05-261-2/+2
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* | | | | | | | Merge pull request #2090 from whitequark/cxxrtl-fixeswhitequark2020-05-261-7/+13
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| * | | | | | | cxxrtl: make logging a little bit nicer.whitequark2020-05-261-2/+10
| * | | | | | | cxxrtl: add missing parts of commit 281c9685.whitequark2020-05-261-5/+3
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* | | | | | | Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidyEddie Hung2020-05-253-13/+15
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| * | | | | | tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
| * | | | | | xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* | | | | | Merge pull request #2044 from YosysHQ/eddie/fix2037Eddie Hung2020-05-252-20/+85
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| * | | | | verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
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