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* Optionally use ${CC} when compiling test utils.Sergey Kvachonok2016-03-251-1/+1
* Allow redefining pkg-config Makefile command.Sergey Kvachonok2016-03-251-2/+4
* Allow redefining binary and data install locations.Sergey Kvachonok2016-03-251-14/+15
* Do not set "nosync" on task outputs, fixes #134Clifford Wolf2016-03-241-1/+2
* Fixed handling of inverters (aka 1-input luts) in nlutmapClifford Wolf2016-03-231-2/+2
* Added GP_DFFS, GP_DFFR, and GP_DFFSRClifford Wolf2016-03-234-21/+76
* Added GP_DFF INIT parameterClifford Wolf2016-03-232-0/+4
* Added ast.h to exported headersClifford Wolf2016-03-221-0/+1
* Cleanup abstract modules at end of "hierarchy -top"Clifford Wolf2016-03-211-2/+0
* Support for abstract modules in chparamClifford Wolf2016-03-211-0/+6
* Added support for $stop system taskClifford Wolf2016-03-211-5/+5
* Improvements in synth_greenpak4, added -part optionClifford Wolf2016-03-211-30/+25
* Improvements in ABCEXTERNAL handlingClifford Wolf2016-03-193-11/+18
* Merge pull request #130 from ravenexp/masterClifford Wolf2016-03-192-4/+16
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| * Support calling out to an external ABC.Sergey Kvachonok2016-03-192-4/+16
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* Added $display %m support, fixed mem leak in $display, fixes #128Clifford Wolf2016-03-191-20/+44
* Added black box modules for all the 7-series design elements (as listed in ug...Clifford Wolf2016-03-194-0/+3441
* Fixed localparam signdness, fixes #127Clifford Wolf2016-03-181-1/+1
* Set "nosync" attribute on internal task/function wiresClifford Wolf2016-03-181-0/+1
* Fixed Verilog parser fix and more similar improvementsClifford Wolf2016-03-151-18/+9
* Use left-recursive rule for cell_port_list in Verilog parser.Andrew Becker2016-03-151-6/+10
* Bugfix in write_verilog for RTLIL processesClifford Wolf2016-03-141-9/+20
* Cleanups and improvements in examples/cmos/Clifford Wolf2016-03-115-12/+19
* Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'Clifford Wolf2016-03-115-9/+76
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| * Completed ngspice digital example with verilog tbUros Platise2016-03-055-9/+76
* | Fixed typos in verilog_defaults help messageClifford Wolf2016-03-101-3/+3
* | Added "write_edif -nogndvcc"Clifford Wolf2016-03-081-17/+34
* | Added examples/cxx-api/evaldemo.ccClifford Wolf2016-03-081-0/+55
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-03-077-25/+123
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| * Added digital (xspice) example code to examples/cmos/Clifford Wolf2016-03-024-1/+70
| * Be more conservative with net names in spice outputClifford Wolf2016-03-021-18/+47
| * Merge pull request #119 from SebKuzminsky/spelling-fixesClifford Wolf2016-02-292-6/+6
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| | * user-facing spelling fixesSebastian Kuzminsky2016-02-282-6/+6
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* / Using "mfs" and "lutpack" in ABC lut mappingClifford Wolf2016-03-071-5/+14
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* We are now in 0.6+ developmentClifford Wolf2016-02-261-1/+1
* Yosys 0.6Clifford Wolf2016-02-261-1/+1
* Fixed BLIF parser for empty port assignmentsClifford Wolf2016-02-241-2/+2
* Use easyer-to-read unoptimized ceil_log2()Clifford Wolf2016-02-151-18/+5
* Updated ABC to ae7d65e71adcClifford Wolf2016-02-151-1/+1
* Updated command reference in manualClifford Wolf2016-02-143-16/+364
* Changelog for upcoming 0.6 releaseClifford Wolf2016-02-141-0/+88
* Fixed more visual studio warningsClifford Wolf2016-02-141-5/+3
* Fixed some visual studio warningsClifford Wolf2016-02-138-10/+10
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-02-131-1/+1
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| * Fixed MXE ABC buildClifford Wolf2016-02-131-1/+1
* | Added "int ceil_log2(int)" functionClifford Wolf2016-02-135-10/+58
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* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
* Support for more Verific primitives (patch I got per email)Clifford Wolf2016-02-131-1/+31
* Updated ABCClifford Wolf2016-02-081-1/+1
* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
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