iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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* \| \| \|	Merge pull request #1850 from boqwxp/cleanup_backends	Eddie Hung	2020-04-01	7	-103/+84
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\| * \| \| \|	Update `RTLIL::id2cstr()` usage to `log_id`.	Alberto Gonzalez	2020-04-01	1	-2/+2
\| * \| \| \|	Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`.	Alberto Gonzalez	2020-04-01	1	-22/+19
\| * \| \| \|	Clean up pseudo-private member usage in `backends/blif/blif.cc`.	Alberto Gonzalez	2020-04-01	1	-15/+11
\| * \| \| \|	Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`.	Alberto Gonzalez	2020-04-01	1	-22/+19
\| * \| \| \|	Clean up pseudo-private member usage in `backends/spice/spice.cc`.	Alberto Gonzalez	2020-04-01	1	-13/+9
\| * \| \| \|	Clean up pseudo-private member usage in `backends/edif/edif.cc`.	Alberto Gonzalez	2020-04-01	1	-23/+18
\| * \| \| \|	Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`.	Alberto Gonzalez	2020-04-01	1	-6/+6
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* \| \| \|	Merge pull request #1848 from YosysHQ/eddie/fix_dynslice	Claire Wolf	2020-04-01	2	-1/+13
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\| * \| \| \|	ast: simplify to fully populate dynamic slicing case transformation	Eddie Hung	2020-03-31	1	-1/+1
\| * \| \| \|	Add dynamic slicing Verilog testcase	Eddie Hung	2020-03-31	1	-0/+12
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* \| \| \|	Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup	Eddie Hung	2020-03-31	3	-132/+194
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\| * \| \|	opt_merge: unordered_map -> dict as per @cliffordwolf review	Eddie Hung	2020-03-16	1	-1/+1
\| * \| \|	opt_merge: speedup	Eddie Hung	2020-03-16	3	-132/+194
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* \| \|	Merge pull request #1783 from boqwxp/astcc_cleanup	Eddie Hung	2020-03-30	1	-13/+20
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\| * \| \|	Add explanatory comment about inefficient wire removal and remove superfluous...	Alberto Gonzalez	2020-03-30	1	-4/+8
\| * \| \|	Revert over-aggressive change to a more modest cleanup.	Alberto Gonzalez	2020-03-27	1	-2/+3
\| * \| \|	Clean up pseudo-private member usage in `frontends/ast/ast.cc`.	Alberto Gonzalez	2020-03-19	1	-11/+13
* \| \| \|	Merge pull request #1835 from boqwxp/cleanup_sat_expose	Eddie Hung	2020-03-30	1	-85/+66
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\| * \| \|	Remove unused function parameter.	Alberto Gonzalez	2020-03-30	1	-2/+2
\| * \| \|	Simplify iterating over selected modules or cells.	Alberto Gonzalez	2020-03-30	1	-16/+4
\| * \| \|	Clean up more in `passes/sat/expose.cc`.	Alberto Gonzalez	2020-03-30	1	-64/+59
\| * \| \|	Clean up pseudo-private member usage in `passes/sat/expose.cc`.	Alberto Gonzalez	2020-03-28	1	-11/+9
* \| \| \|	Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design	Eddie Hung	2020-03-30	1	-31/+33
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\| * \| \| \|	Replace `RTLIL::id2cstr()` with `log_id()`.	Alberto Gonzalez	2020-03-30	1	-1/+1
\| * \| \| \|	Clean up pseudo-private member usage in `passes/cmds/design.cc`.	Alberto Gonzalez	2020-03-28	1	-31/+33
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* \| \| \|	Merge pull request #1786 from boqwxp/hierarchycc_cleanup	Eddie Hung	2020-03-30	1	-69/+63
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\| * \| \| \|	Fix double deletion in `passes/hierarchy/hierarchy.cc`.	Alberto Gonzalez	2020-03-30	1	-1/+0
\| * \| \| \|	Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.	Alberto Gonzalez	2020-03-19	1	-68/+63
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* \| \| \|	Merge pull request #1831 from boqwxp/cleanup_sat_eval	Eddie Hung	2020-03-30	1	-46/+44
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\| * \| \| \|	Further clean up `passes/sat/eval.cc`.	Alberto Gonzalez	2020-03-30	1	-16/+15
\| * \| \| \|	Clean up pseudo-private member usage in `passes/sat/eval.cc`.	Alberto Gonzalez	2020-03-28	1	-35/+34
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* \| \| \|	Merge pull request #1833 from boqwxp/cleanup_sat_freduce	Eddie Hung	2020-03-30	1	-15/+13
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\| * \| \| \|	Further clean up `passes/sat/freduce.cc`.	Alberto Gonzalez	2020-03-30	1	-3/+2
\| * \| \| \|	Clean up pseudo-private member usage in `passes/sat/freduce.cc`.	Alberto Gonzalez	2020-03-28	1	-13/+12
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* \| \| \|	Merge pull request #1811 from PeterCrozier/typedef_scope	N. Engelhardt	2020-03-30	6	-43/+88
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\| * \| \| \|	Inline productions to follow house style.	Peter Crozier	2020-03-27	1	-33/+29
\| * \| \| \|	Error duplicate declarations of a typedef name in the same scope.	Peter Crozier	2020-03-24	2	-3/+11
\| * \| \| \|	Support module/package/interface/block scope for typedef names.	Peter Crozier	2020-03-23	6	-22/+63
* \| \| \| \|	Merge pull request #1778 from rswarbrick/sv-defines	N. Engelhardt	2020-03-30	11	-151/+636
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\| * \| \| \| \|	Add support for SystemVerilog-style `define to Verilog frontend	Rupert Swarbrick	2020-03-27	11	-151/+636
* \| \| \| \| \|	Explicit include of csignal	Miodrag Milanovic	2020-03-28	1	-0/+1
* \| \| \| \| \|	windows - there are no stopping signals	Miodrag Milanovic	2020-03-28	1	-0/+1
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* \| \| \| \|	Merge pull request #1607 from whitequark/simplify-simplify-meminit	Claire Wolf	2020-03-27	1	-63/+82
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\| * \| \| \|	ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.	whitequark	2020-02-07	1	-65/+84
* \| \| \| \|	Merge pull request #1815 from boqwxp/fix-ef-optimize	Claire Wolf	2020-03-27	1	-1/+7
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\| * \| \| \| \|	Do not change solver output parsing for non-exists-forall problems.	Alberto Gonzalez	2020-03-26	1	-2/+6
\| * \| \| \| \|	Skip reading stdout from the solver that if it isn't a line reading only "sat...	Alberto Gonzalez	2020-03-26	1	-1/+3
* \| \| \| \| \|	Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix	Claire Wolf	2020-03-26	2	-1/+19
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\| * \| \| \| \|	techmap: Fix cell names with _TECHMAP_REPLACE_.*	Marcin Kościelnicki	2020-03-23	2	-1/+19