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* Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-300-0/+0
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| * Get rid of holes_modeEddie Hung2019-12-301-70/+35
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* | Remove abc9 -clk optionEddie Hung2019-12-301-1/+1
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* | abc9_ops -prep_dff cope with lack of holes moduleEddie Hung2019-12-301-38/+38
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* | Rename structEddie Hung2019-12-301-3/+3
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* | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-302-13/+4
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| * Add -D DFF_MODE to abc9_map testEddie Hung2019-12-301-4/+4
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| * Remove delay targets docEddie Hung2019-12-301-9/+0
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* | Move Pass::call() out of abc9_ops into abc9Eddie Hung2019-12-303-68/+63
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* | CleanupEddie Hung2019-12-301-7/+3
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* | Use function argEddie Hung2019-12-301-9/+9
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* | holes_module to be whiteboxEddie Hung2019-12-301-0/+10
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* | Rid unnecessary ifEddie Hung2019-12-301-13/+11
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* | Get rid of holes_modeEddie Hung2019-12-301-70/+35
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* | Add abc9_ops -prep_holesEddie Hung2019-12-303-135/+321
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* | Add abc9_ops -prep_dffEddie Hung2019-12-303-39/+50
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* | Restore count_outputs, move process check to abcEddie Hung2019-12-302-11/+13
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* | Fix struct nameEddie Hung2019-12-301-3/+3
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* | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-3018-751/+1411
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| * write_xaiger to use scratchpad for stats; cleanup abc9Eddie Hung2019-12-302-190/+20
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| * Remove submod changesEddie Hung2019-12-302-201/+37
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| * Remove unusedEddie Hung2019-12-301-5/+0
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| * Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
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| * Call "proc" if processes inside whiteboxesEddie Hung2019-12-301-1/+1
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| * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3042-211/+1731
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| * | Add CHANGELOG entry, add abc9_{flop,keep} attr to README.mdEddie Hung2019-12-302-0/+7
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| * | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
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| * | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-304-53/+120
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| * | GrammarEddie Hung2019-12-301-1/+1
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| * | Really fix it!Eddie Hung2019-12-271-10/+7
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| * | write_xaiger: fix arrival times for non boxesEddie Hung2019-12-271-18/+25
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| * | Disable clock domain partitioning in Yosys pass, let ABC do itEddie Hung2019-12-231-6/+22
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| * | write_xaiger to opt instead of just clean whiteboxesEddie Hung2019-12-231-1/+1
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| * | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-2011-216/+339
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| * | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
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| * | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-196-41/+60
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1947-161/+2030
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| * | | | | Bump ABC againEddie Hung2019-12-181-1/+1
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| * | | | | Remove &verify -sEddie Hung2019-12-171-1/+1
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| * | | | | Bump ABC for upstream fixEddie Hung2019-12-171-1/+1
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| * | | | | Use pool<> instead of std::set<> to preserver orderingEddie Hung2019-12-171-6/+6
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| * | | | | aiger frontend to user shorter, $-prefixed, namesEddie Hung2019-12-171-14/+14
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| * | | | | Cleanup xaiger, remove unnecessary complexity with inoutEddie Hung2019-12-172-84/+24
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| * | | | | read_xaiger to cope with optional '\n' after 'c'Eddie Hung2019-12-171-2/+2
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| * | | | | Do not sigmapEddie Hung2019-12-171-1/+1
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| * | | | | Revert "Use sigmap signal"Eddie Hung2019-12-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 42f990f3a6b7928841fa0e290fa2688925485907.
| * | | | | abc9 needs a clean afterwardsEddie Hung2019-12-161-2/+4
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| * | | | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flopEddie Hung2019-12-161-5/+27
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| * | | | | Use sigmap signalEddie Hung2019-12-161-1/+1
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