iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed handling of re-declarations of wires in tasks and functions	Clifford Wolf	2015-11-23	1	-7/+26
*	Added torder command	Clifford Wolf	2015-11-19	2	-0/+124
*	Fixed performance bug in Verific importer	Clifford Wolf	2015-11-16	1	-10/+12
*	Changes for Verific 3.16_484_32_151112	Clifford Wolf	2015-11-12	3	-4/+7
*	Link to vlsitechnology.org for liberty files	Clifford Wolf	2015-11-12	1	-6/+4
*	More bugfixes in handling of parameters in tasks and functions	Clifford Wolf	2015-11-12	2	-2/+23
*	Fixed handling of parameters and localparams in functions	Clifford Wolf	2015-11-11	4	-5/+39
*	Added "abc -g"	Clifford Wolf	2015-11-10	1	-11/+48
*	Merge pull request #97 from zeldin/master	Clifford Wolf	2015-11-08	1	-1/+1
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\| *	Fix a segfault in dffinit when the value has too few bits	Marcus Comstedt	2015-11-08	1	-1/+1
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*	Added "singleton" pass	Clifford Wolf	2015-11-07	2	-0/+102
*	Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling	Clifford Wolf	2015-11-06	1	-2/+2
*	Bugfix in mapping $tribuf to $_TBUF_	Clifford Wolf	2015-11-05	1	-1/+1
*	Bugfix in memory_dff	Clifford Wolf	2015-10-31	2	-1/+27
*	Improvements in wreduce	Clifford Wolf	2015-10-31	2	-0/+34
*	Bugfix in Xilinx LUT mapping	Clifford Wolf	2015-10-30	1	-1/+1
*	Improved SigMap performance	Clifford Wolf	2015-10-28	3	-5/+16
*	Improvements in new SigMap	Clifford Wolf	2015-10-28	1	-5/+16
*	Use mfp<> in equiv_mark	Clifford Wolf	2015-10-27	1	-28/+4
*	Removed old SigMap implementation	Clifford Wolf	2015-10-27	1	-224/+0
*	Added hashlib::mfp and new SigMap	Clifford Wolf	2015-10-27	3	-0/+185
*	Improvements in equiv_struct	Clifford Wolf	2015-10-25	1	-17/+62
*	Major refactoring of equiv_struct	Clifford Wolf	2015-10-25	2	-93/+170
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	39	-161/+168
*	Added "equiv_add -cell"	Clifford Wolf	2015-10-25	2	-34/+95
*	equiv_struct now creates equiv_merged attributes	Clifford Wolf	2015-10-25	1	-0/+3
*	Improvements in equiv_struct	Clifford Wolf	2015-10-24	1	-1/+22
*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24	8	-34/+34
*	improvement in "stat"	Clifford Wolf	2015-10-24	1	-1/+1
*	Fixed driver conflict handling (various cmds)	Clifford Wolf	2015-10-24	1	-3/+12
*	equiv_purge bugfix, using SigChunk in Yosys namespace	Clifford Wolf	2015-10-24	5	-5/+8
*	Fixed handling of driver-driver conflicts in wreduce	Clifford Wolf	2015-10-24	3	-9/+42
*	Added equiv_mark command	Clifford Wolf	2015-10-23	3	-1/+265
*	Disabled "Skipping blackbox module" msg in show command	Clifford Wolf	2015-10-23	1	-1/+1
*	Added support for ":" as comment symbol after ;-parsing	Clifford Wolf	2015-10-23	1	-1/+1
*	Also merge $equiv cells in equiv_struct	Clifford Wolf	2015-10-23	1	-0/+1
*	Improvements in equiv_struct	Clifford Wolf	2015-10-23	1	-11/+18
*	Added equiv_purge	Clifford Wolf	2015-10-22	2	-0/+210
*	Added equiv_struct command	Clifford Wolf	2015-10-21	2	-0/+188
*	Improved inout handling in equiv_make	Clifford Wolf	2015-10-21	1	-1/+1
*	Progress on cell help messages	Clifford Wolf	2015-10-20	1	-18/+114
*	Progress on cell help messages	Clifford Wolf	2015-10-17	3	-54/+107
*	Progress in yosys-smtbmc	Clifford Wolf	2015-10-15	1	-4/+10
*	Fixed bug in verilog parser	Clifford Wolf	2015-10-15	1	-1/+1
*	Improvements in yosys-smtbmc	Clifford Wolf	2015-10-15	3	-2/+9
*	Bugfixes in handling of "keep" attribute on wires	Clifford Wolf	2015-10-15	2	-2/+8
*	More "yosys-smtbmc -c" fixes	Clifford Wolf	2015-10-14	2	-9/+30
*	Fixed yosys-smtbmc -c	Clifford Wolf	2015-10-14	1	-2/+2
*	Added "prep" command	Clifford Wolf	2015-10-14	2	-0/+157
*	Added more cell descriptions	Clifford Wolf	2015-10-14	1	-0/+85