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* Some driver changes/fixesClifford Wolf2013-11-221-5/+5
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* Fixed O(n^2) performance bug in verilog preprocessorClifford Wolf2013-11-221-1/+1
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* Added more performance measurement infrastructureClifford Wolf2013-11-222-2/+43
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* Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵Clifford Wolf2013-11-225-24/+3
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* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-221-30/+13
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* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-222-24/+119
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* Improved make rules for profiling and debuggingClifford Wolf2013-11-221-3/+3
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* Updated abcClifford Wolf2013-11-214-11/+39
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* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-211-1/+44
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* Fixed async proc detection in mem2regClifford Wolf2013-11-211-5/+9
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-2110-89/+375
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* Fixed a bug in "add -global_input"Clifford Wolf2013-11-211-16/+17
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* Added "proc_arst -global_arst" featureClifford Wolf2013-11-202-8/+81
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* Fixed ilang parser: memory widthClifford Wolf2013-11-201-1/+1
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* Added "add" command (only wires for now)Clifford Wolf2013-11-202-0/+155
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* Another name resolution bugfix for generate blocksClifford Wolf2013-11-202-4/+61
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* Implemented indexed part selectsClifford Wolf2013-11-204-3/+19
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* Do not allow memory bit select on the left side of an assignmentClifford Wolf2013-11-201-1/+1
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* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-201-6/+6
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* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-202-3/+16
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* Implemented part/bit select on memory readClifford Wolf2013-11-204-5/+104
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* Updated TODOs in README fileClifford Wolf2013-11-201-6/+26
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* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-202-6/+23
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* Added "make config-sudo"Clifford Wolf2013-11-191-6/+10
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* Install simlib in datdirClifford Wolf2013-11-191-0/+6
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* Large improvements in yosys-configClifford Wolf2013-11-193-17/+84
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* Fixed parsing of module arguments when one type is used for many argsClifford Wolf2013-11-191-3/+10
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* Renamed temp module generated by "abc" pass from "logic" to "netlist"Clifford Wolf2013-11-192-6/+6
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* Added additional mem2reg testcaseClifford Wolf2013-11-181-0/+28
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* Fixed two bugs in mem2reg functionality in AST frontendClifford Wolf2013-11-181-4/+8
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* Added dumping of attributes in AST frontendClifford Wolf2013-11-181-0/+11
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* Fixed parsing of default cases when not last caseClifford Wolf2013-11-182-12/+38
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* Fixed mem2reg for reg usage outside always blockClifford Wolf2013-11-181-1/+1
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* Added commented-out osu025 maping commands to cmos techmap exampleClifford Wolf2013-11-181-0/+5
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* Added -v<level> option and some minor driver cleanupsClifford Wolf2013-11-173-5/+23
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* Renamed ABCHGPULL to ABCPULL in MakefileClifford Wolf2013-11-161-2/+2
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* Improved building of yosys-abcClifford Wolf2013-11-131-1/+5
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* Fixed abc pass blif parser for constant bitsClifford Wolf2013-11-131-18/+57
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* Fixed parsing of "parameter integer"Clifford Wolf2013-11-131-2/+2
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* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-115-52/+52
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* Added information on all internal cell types to internal checkerClifford Wolf2013-11-111-0/+340
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* Call internal checker more oftenClifford Wolf2013-11-104-9/+11
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* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-094-20/+31
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* Silenced a gcc warning in spice backendClifford Wolf2013-11-091-1/+1
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* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-092-6/+48
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* More undef-propagation related fixesClifford Wolf2013-11-082-0/+9
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* Fixed handling of different signedness in power operandsClifford Wolf2013-11-081-1/+1
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* Fixed keep attribute on wires in opt_cleanClifford Wolf2013-11-081-1/+1
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* Implemented const folding of ternary op with undef selectClifford Wolf2013-11-081-0/+8
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* Removed debug log from const_pow()Clifford Wolf2013-11-081-1/+0
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