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| | * | fsm_export: optionally use binary state encoding as state names instead ofJohann Glaser2013-04-051-6/+23
| | | | | | | | | | | | | | | | s0, s1, ...
| * | | Merge pull request #4 from hansiglaser/masterClifford Wolf2013-04-051-5/+20
| |\| | | | | | | | | | fsm_export: specify KISS filename on command line
| | * | fsm_export: specify KISS filename on command lineJohann Glaser2013-04-051-5/+20
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* / / Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-071-4/+4
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* | Fixed/improved handling of colored wires in show commandClifford Wolf2013-04-011-2/+2
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* | Added support for @<set-name> in expand select ops (%x, %ci, %co)Clifford Wolf2013-04-011-2/+12
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* | Removed 4096 bytes limit for size of command from script fileClifford Wolf2013-04-011-3/+20
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* | Added -color <color> <selection> option to show commandClifford Wolf2013-04-014-22/+101
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* | Fixed "select" for "%%" stmt with emty stackClifford Wolf2013-03-311-1/+2
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* | Added "script" commandClifford Wolf2013-03-311-0/+16
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* | Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-315-21/+32
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* | Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-315-3/+15
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* | Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-316-0/+111
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* | Added k68 (m68k compatible cpu) test case from verilatorClifford Wolf2013-03-313-0/+61
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* | Improved opt_share for reduce cellsClifford Wolf2013-03-293-3/+32
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* | Improved opt_share for commutative standard cellsClifford Wolf2013-03-291-1/+28
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* | Added EXTRA_TARGETS Makefile variableClifford Wolf2013-03-282-2/+3
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* | Improved Makefile: Added ENABLE_* switchesClifford Wolf2013-03-281-8/+24
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* | Implemented TCL support (only via -c option at the moment)Clifford Wolf2013-03-285-9/+83
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* | Improved subcircuit verbose output (added portmapper results)Clifford Wolf2013-03-281-0/+15
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* | Fixed svgviewer hacks for builtin filesClifford Wolf2013-03-281-8/+9
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* | Added proper TECHMAP_FAIL support and added support for the celltype ↵Clifford Wolf2013-03-281-84/+129
| | | | | | | | attribute in the map file
* | Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-287-16/+70
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* | Keep viewport transform stable on reload in yosys-svgviewerClifford Wolf2013-03-272-4/+8
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* | Added check: only one module for "show" unless format is "ps"Clifford Wolf2013-03-271-0/+9
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* | Now using SVG and yosys-svgviewer per default in show commandClifford Wolf2013-03-274-16/+67
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* | Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlibClifford Wolf2013-03-274-5/+18
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* | Imported svgviewer from qt4.8Clifford Wolf2013-03-2711-0/+994
| | | | | | | | | | This is from commit 543486a41963f8d20d9771d2107cdd5a22894bdb in the Qt git repository: git://gitorious.org/qt/qt.git
* | Create nice errors when calling RTLIL::Module::derive() of base classClifford Wolf2013-03-261-3/+3
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* | Collect parameters in hierarchy -generate (and do nothing with them)Clifford Wolf2013-03-261-1/+8
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* | Tiny bugfix in simlib.vClifford Wolf2013-03-261-1/+0
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* | Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-262-4/+2
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* | Fixed handling of unconditional generate blocksClifford Wolf2013-03-262-1/+19
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* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-255-34/+27
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* Improved verbose output of subcircuitClifford Wolf2013-03-251-1/+11
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* Improved method for finding fsm_expand candidatesClifford Wolf2013-03-251-5/+7
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* Added hierarchy -generate command for generating skeletton modulesClifford Wolf2013-03-252-4/+172
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* Changed fsm_expand to merge multiplexers more aggressivelyClifford Wolf2013-03-241-1/+4
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* Renamed hansimem.v test case to mem_arst.vClifford Wolf2013-03-241-1/+0
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* Fixed handling of show -viewerClifford Wolf2013-03-241-1/+1
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* Fixed handling of internal signals in show commandClifford Wolf2013-03-241-2/+2
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* Improved show -colors color assignmentsClifford Wolf2013-03-241-2/+3
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* Added show -strech and renamed -widthlabels to -widthClifford Wolf2013-03-241-6/+36
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* Added -widthlabels options to chow commandClifford Wolf2013-03-241-31/+67
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* Added -notypes option to intersynth backendClifford Wolf2013-03-241-7/+18
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* Reorganized TODOsClifford Wolf2013-03-241-24/+13
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* Added mem2reg option to verilog frontendClifford Wolf2013-03-245-11/+31
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* Fixed stdcells.v for $adff with undef reset valueClifford Wolf2013-03-241-63/+68
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* Another fix in mem2reg ast simplify logicClifford Wolf2013-03-241-1/+3
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* Added -colors option to show commandClifford Wolf2013-03-241-8/+35
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