aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* More ABC releated Makefile changesClifford Wolf2013-12-041-1/+10
|
* Minor improvements in ABc buildClifford Wolf2013-12-031-8/+3
|
* Progress on AppNote 011Clifford Wolf2013-12-025-3/+77
|
* Fixed submod for non-primitive cellsClifford Wolf2013-12-021-0/+1
|
* Fixed submod for non-cleaned designsClifford Wolf2013-12-021-1/+4
|
* Added Pass:call_newsel APIClifford Wolf2013-12-022-0/+27
|
* Added "history" commandClifford Wolf2013-12-021-0/+18
|
* A fix in memory_dff for write ports with static addressesClifford Wolf2013-12-011-10/+10
|
* Progress on AppNote 011Clifford Wolf2013-12-014-24/+200
|
* Progress on AppNote 011Clifford Wolf2013-11-296-16/+110
|
* Progress on AppNote 011Clifford Wolf2013-11-296-11/+190
|
* Using RTLIL::id2cstr for prompt printingClifford Wolf2013-11-291-1/+1
|
* Added dump -m and -n optionsClifford Wolf2013-11-292-54/+89
|
* Progress on AppNote 011Clifford Wolf2013-11-284-58/+143
|
* Merge pull request #17 from mschmoelzer/masterClifford Wolf2013-11-281-0/+1
|\ | | | | Include unistd.h in svgview.cpp (required for getcwd() function)
| * Include unistd.h in svgview.cpp (required for getcwd() function)Martin Schmölzer2013-11-281-0/+1
| | | | | | | | | | | | This fixes compilation on Arch Linux, which otherwise fails. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
* | Fixed temp net name generation in rtlil process generator for abbreviated ↵Clifford Wolf2013-11-281-0/+2
| | | | | | | | name matching
* | Added pattern support to "ls" commandClifford Wolf2013-11-281-30/+35
| |
* | Improved ID matching scheme in select (and thus for all commands)Clifford Wolf2013-11-281-2/+12
| |
* | Fixes and improvements in "show" commandClifford Wolf2013-11-281-10/+42
| |
* | More progress on AppNote 011Clifford Wolf2013-11-284-5/+122
| |
* | Added "src" attribute to processesClifford Wolf2013-11-282-1/+5
| |
* | Started writing appnote 011Clifford Wolf2013-11-287-3/+157
| |
* | Added support for "show -pause" and "show -format dot"Clifford Wolf2013-11-281-6/+30
|/
* Added QGraphicsWebView to yosys-svgviewerClifford Wolf2013-11-284-16/+58
|
* Updated ABC to 9241719523f6Clifford Wolf2013-11-281-5/+5
|
* Added some svgviewer code for possible future switch to QGraphicsWebViewClifford Wolf2013-11-273-6/+20
|
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-271-1/+1
|\
| * Set version number to 0.1.0+Clifford Wolf2013-11-271-1/+1
| |
* | Tighter integration of ABC buildClifford Wolf2013-11-274-7/+35
|/
* Started implementing undef support in "sat" commandClifford Wolf2013-11-251-12/+103
|
* Bugfixes in new "stat" commandClifford Wolf2013-11-251-7/+1
|
* Added "stat" commandClifford Wolf2013-11-252-0/+219
|
* Improvements in satgen undef handlingClifford Wolf2013-11-252-87/+209
|
* Improvements in satgen undef handlingClifford Wolf2013-11-252-31/+142
|
* Added ezsat vec_const() apiClifford Wolf2013-11-252-17/+26
|
* Started implementing undef handling in satgenClifford Wolf2013-11-252-34/+202
|
* Removed undef feature from ezsat apiClifford Wolf2013-11-252-11/+2
|
* Using simplemap mappers from techmapClifford Wolf2013-11-243-742/+104
|
* Added simplemap passClifford Wolf2013-11-242-0/+518
|
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-246-22/+25
|
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-243-3/+14
|
* Added techmap -D and -I optionsClifford Wolf2013-11-241-2/+16
|
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-243-5/+19
|
* Added "techmap -share_map" optionClifford Wolf2013-11-242-4/+13
|
* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-241-0/+5
|
* Updated TODOsClifford Wolf2013-11-241-2/+1
|
* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-241-1/+1
|
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-241-4/+6
|
* Added support for signed parameters in ilangClifford Wolf2013-11-243-2/+9
|