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| * | | | cxxrtl: provide a way to perform unobtrusive power-on reset.whitequark2020-12-024-3/+78
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although it is always possible to destroy and recreate the design to simulate a power-on reset, this has two drawbacks: * Black boxes are also destroyed and recreated, which causes them to reacquire their resources, which might be costly and/or erase important state. * Pointers into the design are invalidated and have to be acquired again, which is costly and might be very inconvenient if they are captured elsewhere (especially through the C API).
* | | | Merge pull request #2456 from Zottel/masterwhitequark2020-12-021-0/+1
|\ \ \ \ | | | | | | | | | | Return correct modname when found in cache.
| * | | | Return correct modname when found in cache.Julius Roob2020-11-261-0/+1
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* | | | | Merge pull request #2455 from gsomlo/gls-fedpkg-fixeswhitequark2020-12-022-0/+6
|\ \ \ \ \ | | | | | | | | | | | | Fixes for building Fedora distro RPMs of yosys
| * | | | | fixup over commit 829b5cca to re-enable ABCEXTERNAL supportGabriel Somlo2020-11-261-0/+5
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| * | | | | Add #include needed to build with gcc-11Gabriel Somlo2020-11-261-0/+1
| |/ / / / | | | | | | | | | | | | | | | Suggested by Jeff Law <law@redhat.com>
* | | | | Merge pull request #2467 from YosysHQ/dave/nexus-carry-fixDavid Shah2020-12-021-2/+2
|\ \ \ \ \ | | |_|/ / | |/| | | nexus: More efficient CO mapping
| * | | | nexus: More efficient CO mappingDavid Shah2020-12-021-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #2446 from RobertBaruch/rtlil_formatwhitequark2020-12-023-0/+307
|\ \ \ \ \ | | | | | | | | | | | | Adds appendix on RTLIL text format
| * | | | | Further juggles the wording of "character".Robert Baruch2020-11-251-1/+1
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| * | | | | Clarifies how character encodings work.Robert Baruch2020-11-251-5/+5
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| * | | | | Clarifies whitespace and eol.Robert Baruch2020-11-251-2/+6
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| * | | | | Cleans up doublequotesRobert Baruch2020-11-251-2/+2
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| * | | | | Clarifies use of integers, and character set.Robert Baruch2020-11-251-4/+12
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| * | | | | Clarifies processes, corrects some attributesRobert Baruch2020-11-251-29/+46
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| * | | | | Refactors for attributes.Robert Baruch2020-11-241-50/+50
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| * | | | | Cleans up some descriptions and syntaxRobert Baruch2020-11-241-25/+43
| | | | | | | | | | | | | | | | | | Now all rules ending in "-stmt" end in eol.
| * | | | | Adds missing "end" and eol to module.Robert Baruch2020-11-221-1/+1
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| * | | | | Update to Values #2Robert Baruch2020-11-221-1/+1
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| * | | | | Update to Values sectionRobert Baruch2020-11-221-2/+2
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| * | | | | Adds appendix on RTLIL text formatRobert Baruch2020-11-223-0/+260
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* | | | | | Bump required Verific versionMiodrag Milanovic2020-12-021-1/+1
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* | | | | | Bump versionYosys Bot2020-12-021-1/+1
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* | | | | Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_definesClaire Xen2020-12-012-1/+3
|\ \ \ \ \ | |_|/ / / |/| | | | Fix SYNTHESIS always being defined in Verilog frontend
| * | | | Fix SYNTHESIS always being defined in Verilog frontendgeorgerennie2020-12-012-1/+3
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* | | | Merge pull request #2460 from pepijndevos/simple-gowinMiodrag Milanović2020-12-011-3/+32
|\ \ \ \ | |/ / / |/| | | add -noalu and -json option for apicula
| * | | add -noalu and -json option for apiculaPepijn de Vos2020-11-301-3/+32
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* | | Bump versionYosys Bot2020-11-261-1/+1
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* | | Merge pull request #2452 from whitequark/rtlil-remove-dot-identifierswhitequark2020-11-251-1/+0
|\ \ \ | | | | | | | | rtlil: remove dotted identifiers
| * | | rtlil: remove dotted identifiers.whitequark2020-11-251-1/+0
| | | | | | | | | | | | | | | | No one knows where they came from and they never did anything useful.
* | | | Merge pull request #2453 from YosysHQ/mmicko/verilog_assignmentsMiodrag Milanović2020-11-251-6/+26
|\ \ \ \ | | | | | | | | | | Generate only simple assignments in verilog backend
| * | | | Add verilog backend option for simple_lhsMiodrag Milanovic2020-11-251-6/+22
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| * | | | generate only simple assignments in verilog backendMiodrag Milanovic2020-11-251-5/+9
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* | | | Merge pull request #2133 from dh73/nodev_headClaire Xen2020-11-2518-65/+322
|\ \ \ \ | | | | | | | | | | Adding latch tests for shift&mask AST dynamic part-select enhancements
| * | | | Removing trailing whitespacediego2020-06-101-30/+30
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| * | | | Adding latch tests for shift&mask AST dynamic part-select enhancementsdiego2020-06-0918-68/+325
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* | | | | Merge pull request #2442 from cr1901/sccachewhitequark2020-11-251-2/+7
|\ \ \ \ \ | | | | | | | | | | | | Makefile: Add disabled-by-default ENABLE_SCCACHE config option.
| * | | | | Makefile: Update ABCREV to bring in sccache fixes.William D. Jones2020-11-241-1/+1
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| * | | | | Makefile: Add disabled-by-default ENABLE_SCCACHE config option.William D. Jones2020-11-191-1/+6
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* | | | | Merge pull request #2450 from nitz/sim-vcd-filenamewhitequark2020-11-251-1/+3
|\ \ \ \ \ | | | | | | | | | | | | Add rewrite_filename for sim -vcd argument.
| * | | | | Add rewrite_filename for sim -vcd argument.Chris Dailey2020-11-241-1/+3
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* | | | | Bump versionYosys Bot2020-11-251-1/+1
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* | | | | Merge pull request #2428 from whitequark/check-processeswhitequark2020-11-241-22/+55
|\ \ \ \ \ | | | | | | | | | | | | check: add support for processes
| * | | | | check: add support for processes.whitequark2020-11-031-3/+38
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| * | | | | check: reformat log/help text to match most other passeswhitequark2020-11-031-19/+17
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* | | | | | Merge pull request #2448 from nitz/tcl-script-documentation-fixesMiodrag Milanović2020-11-241-0/+2
|\ \ \ \ \ \ | | | | | | | | | | | | | | Tcl script documentation fixes
| * | | | | | tcl -h message only if YOSYS_ENABLE_TCL defined.nitz2020-11-231-0/+2
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* | | | | | Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parametersMiodrag Milanović2020-11-241-58/+294
|\ \ \ \ \ \ | |/ / / / / |/| | | | | Add firrtl backend support for generic parameters in blackbox components
| * | | | | Formatting fixesSahand Kashani2020-11-231-10/+7
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| * | | | | Add support for real-valued parameters + preserve type of parametersSahand Kashani2020-08-061-38/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for real-valued parameters in blackboxes. Additionally, parameters now retain their types are no longer all encoded as strings. There is a caveat with this implementation due to my limited knowledge of yosys, more specifically to how yosys encodes bitwidths of parameter values. The example below can motivate the implementation choice I took. Suppose a verilog component is declared with the following parameters: parameter signed [26:0] test_signed; parameter [26:0] test_unsigned; parameter signed [40:0] test_signed_large; If you instantiate it as follows: defparam <inst_name> .test_signed = 49; defparam <inst_name> .test_unsigned = 40'd35; defparam <inst_name> .test_signed_large = 40'd12; If you peek in the RTLIL::Const structure corresponding to these params, you realize that parameter "test_signed" is being considered as a 32-bit value since it's declared as "49" without a width specifier, even though the parameter is defined to have a maximum width of 27 bits. A similar issue occurs for parameter "test_unsigned" where it is supposed to take a maximum bit width of 27 bits, but if the user supplies a 40-bit value as above, then yosys considers the value to be 40 bits. I suppose this is due to the type being defined by the RHS rather than the definition. Regardless of this, I emit the same widths as what the user specifies on the RHS when generating firrtl IR.
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