| Commit message (Collapse) | Author | Age | Files | Lines |
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satgen: Move importCell out of the header.
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This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
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sf2: Emit CLKINT even if -clkbuf not passed
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This restores pre #2229 behavior.
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anlogic: Fix FF mapping.
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sf2: replace sf2_iobs with {clkbuf,iopad}map
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verilog_backend: in non-SV mode, add a trigger for `always @*`
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This commit only affects translation of RTLIL processes (for which
there is limited support).
Due to the event-driven nature of Verilog, processes like
reg x;
always @*
x <= 1;
may never execute. This can be fixed in SystemVerilog code by using
`always_comb` instead of `always @*`, but in Verilog-2001 the options
are limited. This commit implements the following workaround:
reg init = 0;
reg x;
always @* begin
if (init) begin end
x <= 1;
end
Fixes #2271.
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verilog_backend: add `-sv` option, make `-o <filename>.sv` work
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See #2271.
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anlogic: Use dfflegalize.
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efinix: Nuke efinix_gbuf in favor of clkbufmap.
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cxxrtl: fix typo
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Use "bison -Wall -Werror" for verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Restore #2203 and #2244 and fix parser conflicts
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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This commit fixes S/R conflicts introduced by commit 6f9be93.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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This commit fixes R/R conflicts introduced by commit 7e83a51.
Parameter logic is already defined as part of `param_range_type` rule.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
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This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
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cxxrtl: expose eval() and commit() via the C API
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Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
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Fixes #2258.
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Skipping non-selected wires is unsound in an obvious way.
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Add AST_EDGE support to AstNode::detect_latch()
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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verilog_parser: turn S/R and R/R conflicts into hard errors
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Fixes #2253.
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This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15.
This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405.
This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3.
This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68.
This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
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cxxrtl: add missing extern "C"
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This bug was hidden if a header was generated.
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* Fix #2251 - YosysJS ReferenceError: _memset is not defined.
Add '_memset' in emcc EXPORTED_FUNCTIONS in Makefile.
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- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
buffer
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Add logic type support to parameters
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