| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | Added required structure to implement unit tests | rodrigosiqueira | 2016-12-04 | 5 | -0/+73 | |
| | |/ |/| | | | | | | | | | | | | | | | | | Added modifications inside the main Makefile to refers the unit test Makefile. Added separated Makefile only for compiling unit tests. Added simple example of unit test. Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com> Signed-off-by: Pablo Alejandro <pabloabur@usp.br> Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br> | |||||
| | * | Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF | Andrew Zonenberg | 2016-12-11 | 1 | -1/+9 | |
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| | * | greenpak4: Added support for inferred input/output inverters on latches | Andrew Zonenberg | 2016-12-10 | 1 | -4/+17 | |
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| | * | greenpak4: Can now techmap inferred D latches (without set/reset or output ↵ | Andrew Zonenberg | 2016-12-10 | 3 | -0/+17 | |
| | | | | | | | | | inverter) | |||||
| | * | greenpak4: Inverted D latch cells now have nQ instead of Q as output port ↵ | Andrew Zonenberg | 2016-12-10 | 1 | -15/+15 | |
| | | | | | | | | | name for consistency | |||||
| | * | Added GP_DLATCH and GP_DLATCHI | Andrew Zonenberg | 2016-12-05 | 1 | -0/+18 | |
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| | * | Initial implementation of techlib support for GreenPAK latches. ↵ | Andrew Zonenberg | 2016-12-05 | 2 | -0/+120 | |
| | | | | | | | | | Instantiation only, no behavioral inference yet. | |||||
| | * | Updated help text for synth_greenpak4 | Andrew Zonenberg | 2016-12-05 | 1 | -0/+2 | |
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| * | Added $assert/$assume support to AIGER back-end | Clifford Wolf | 2016-12-03 | 3 | -13/+54 | |
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| * | Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig | Clifford Wolf | 2016-12-03 | 1 | -2/+15 | |
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| * | Updated ABV to hg rev 8b555d9e67cf | Clifford Wolf | 2016-12-01 | 1 | -1/+1 | |
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| * | Added examples/aiger/ | Clifford Wolf | 2016-12-01 | 4 | -0/+53 | |
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| * | Added "yosys-smtbmc --aig" | Clifford Wolf | 2016-12-01 | 1 | -6/+127 | |
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| * | Added support for partially initialized regs to smt2 back-end | Clifford Wolf | 2016-12-01 | 1 | -3/+15 | |
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| * | Added "write_aiger -zinit -symbols -vmap" | Clifford Wolf | 2016-12-01 | 1 | -30/+139 | |
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| * | Added "write_aiger" command | Clifford Wolf | 2016-11-30 | 2 | -0/+398 | |
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| * | Added "design -reset-vlog" | Clifford Wolf | 2016-11-30 | 1 | -7/+32 | |
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| * | Improved equiv_purge log output | Clifford Wolf | 2016-11-29 | 1 | -1/+1 | |
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| * | Bugfix in smt2 back-end for pure checker modules | Clifford Wolf | 2016-11-28 | 1 | -0/+4 | |
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| * | Added support for macros as include file names | Clifford Wolf | 2016-11-28 | 1 | -0/+2 | |
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| * | Bugfix in "read_verilog -D NAME=VAL" handling | Clifford Wolf | 2016-11-28 | 1 | -3/+3 | |
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| * | Removed shebang line from smtio.py, fixes #279 | Clifford Wolf | 2016-11-27 | 1 | -1/+0 | |
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| * | Added wire start_offset and upto handling BLIF back-end | Clifford Wolf | 2016-11-23 | 1 | -1/+1 | |
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| * | Added wire start_offset and upto handling to splitnets cmd | Clifford Wolf | 2016-11-23 | 1 | -2/+8 | |
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| * | Merge pull request #274 from oldtopman/lcurses | Clifford Wolf | 2016-11-22 | 1 | -0/+5 | |
| |\ | | | | | Added optional flag for linking curses with readline. | |||||
| | * | Added optional flag for linking curses with readline. | oldtopman | 2016-11-21 | 1 | -0/+5 | |
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| * | | Added "yosys-smtbmc --append" | Clifford Wolf | 2016-11-22 | 1 | -2/+20 | |
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| * | Merge pull request #272 from AlexDaniel/master | Clifford Wolf | 2016-11-19 | 1 | -63/+64 | |
| |\ | | | | | Markdownify README (№2) | |||||
| | * | Keep lines under 80 characters | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-19 | 1 | -10/+11 | |
| | | | | | | | | | | | Recent README changes added some characters to existing lines, which made them longer than 80 characters. This commit fixes that. | |||||
| | * | Markdownify README even further | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-19 | 1 | -60/+60 | |
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| * | | Improved ABC default scripts | Clifford Wolf | 2016-11-19 | 1 | -17/+34 | |
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| * | | Merge pull request #271 from azidar/bugfix-assign-wmask | Clifford Wolf | 2016-11-19 | 1 | -0/+1 | |
| |\ \ | |/ |/| | Bugfix: include assign to write-mask | |||||
| | * | Bugfix: include assign to write-mask | Adam Izraelevitz | 2016-11-18 | 1 | -0/+1 | |
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| * | More progress in FIRRTL back-end | Clifford Wolf | 2016-11-18 | 3 | -4/+121 | |
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| * | Progress in FIRRTL back-end | Clifford Wolf | 2016-11-18 | 4 | -5/+55 | |
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| * | Added first draft of FIRRTL back-end | Clifford Wolf | 2016-11-17 | 2 | -0/+353 | |
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| * | Cleanups and fixed in write_verilog regarding reg init | Clifford Wolf | 2016-11-16 | 1 | -15/+61 | |
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| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 5 | -17/+65 | |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 6 | -8/+23 | |
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| * | Merge pull request #268 from AlexDaniel/master | Clifford Wolf | 2016-11-13 | 1 | -34/+27 | |
| |\ | | | | | Markdownify README | |||||
| | * | Markdownify README | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-12 | 1 | -34/+27 | |
| |/ | | | | | This is the first commit in series. There are many other things that could be improved, this is just the first renderable version. | |||||
| * | Minor bugfix in submod | Clifford Wolf | 2016-11-09 | 1 | -0/+1 | |
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| * | Progress in examples/gowin/ | Clifford Wolf | 2016-11-08 | 5 | -21/+95 | |
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| * | Indenting fixes in gowin sim cell lib | Clifford Wolf | 2016-11-08 | 1 | -20/+28 | |
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| * | Bugfix in "setundef" pass | Clifford Wolf | 2016-11-08 | 1 | -2/+7 | |
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| * | Added examples/gowin/ | Clifford Wolf | 2016-11-07 | 6 | -0/+57 | |
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| * | Implemented "scc -set_attr" | Clifford Wolf | 2016-11-06 | 1 | -22/+32 | |
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| * | Bugfix in "scc" command | Clifford Wolf | 2016-11-06 | 1 | -9/+11 | |
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| * | Fixed anonymous genblock object names | Clifford Wolf | 2016-11-04 | 1 | -1/+1 | |
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| * | Added hex constant support to write_verilog | Clifford Wolf | 2016-11-03 | 2 | -5/+63 | |
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index : iCE40/yosys | |
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