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* Progress in equiv_simpleClifford Wolf2015-01-212-41/+110
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* Fixed opt_muxtree performance bugClifford Wolf2015-01-211-11/+28
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* Faster "make clean-abc"Clifford Wolf2015-01-201-2/+2
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* README stuffClifford Wolf2015-01-201-2/+3
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* Added equiv_simpleClifford Wolf2015-01-192-0/+188
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* Added equiv_statusClifford Wolf2015-01-192-0/+95
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* Added equiv_make commandClifford Wolf2015-01-194-1/+260
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* Added $equiv cell typeClifford Wolf2015-01-194-2/+33
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-01-181-0/+6
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| * Merge pull request #47 from mschmoelzer/masterClifford Wolf2015-01-181-0/+6
| |\ | | | | | | Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.
| | * Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.Martin Schmölzer2015-01-181-0/+6
| |/ | | | | | | | | | | | | These Makefile targets simply echo the corresponding Makefile variable, simplifying package build scripts. Signed-off-by: Martin Schmölzer <mschmoelzer@gmail.com>
* | Various cleanups in xilinx techlibClifford Wolf2015-01-187-9/+110
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* | Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-186-674/+466
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* improvements in muxtree/select_leaves testClifford Wolf2015-01-181-2/+5
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* Improvements in opt_muxtreeClifford Wolf2015-01-182-35/+58
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* More opt_muxtree cleanupsClifford Wolf2015-01-181-64/+44
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* Added hashlib::idict<>Clifford Wolf2015-01-183-2/+73
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* Various cleanups and improvements in opt_muxtreeClifford Wolf2015-01-181-87/+71
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* Added synth_xilinx -retime -flattenClifford Wolf2015-01-171-2/+28
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* Added support for memories to flatten (techmap)Clifford Wolf2015-01-171-3/+22
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* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-174-2/+106
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* Fixed a bug in opt_muxtree for "mux forests"Clifford Wolf2015-01-171-4/+18
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* Improved opt_muxtreeClifford Wolf2015-01-171-4/+38
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* Optimizing no-op cell->setPort()Clifford Wolf2015-01-171-1/+3
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* Bugfix in dff2dffeClifford Wolf2015-01-161-1/+1
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* Added cells.libClifford Wolf2015-01-162-0/+109
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* Added dff2dffe to synth_xilinxClifford Wolf2015-01-161-0/+2
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* Added more FF types to xilinx/cells.vClifford Wolf2015-01-161-25/+28
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* Fixed xilinx bram clock inverted configClifford Wolf2015-01-161-21/+35
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* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-161-116/+116
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* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-152-2/+30
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* Added "abc -lut w1:w2"Clifford Wolf2015-01-151-5/+21
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* Fixed handling of foo.__TECHMAP_...Clifford Wolf2015-01-151-1/+1
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* Ignoring more system task and functionsClifford Wolf2015-01-152-2/+4
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* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-151-0/+7
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* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-151-3/+9
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* Various cleanups in synth_xilinx commandClifford Wolf2015-01-131-54/+8
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* Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)Clifford Wolf2015-01-131-5/+0
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* Tiny fix in vcdcd.plClifford Wolf2015-01-131-2/+2
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* Small Makefile typo fixClifford Wolf2015-01-131-2/+2
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* Only enable code coverage counters on linuxClifford Wolf2015-01-094-6/+6
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* Merge pull request #46 from utzig/masterClifford Wolf2015-01-083-5/+11
|\ | | | | Fixes building on a Mac using Homebrew as package manager
| * Enable use of homebrew's provided bison if availableFabio Utzig2015-01-081-0/+2
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| * Enable bison to be customizedFabio Utzig2015-01-083-2/+3
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| * Add homebrew's libffi pathsFabio Utzig2015-01-081-0/+3
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| * Add homebrew's readline pathsFabio Utzig2015-01-081-3/+3
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* Added add_share_file Makefile macroClifford Wolf2015-01-083-38/+17
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* added minimalistic xilinx sim modelsClifford Wolf2015-01-081-0/+150
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* disabled problematic mux -> and/or transformClifford Wolf2015-01-071-2/+7
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* More Xilinx bram cleanupsClifford Wolf2015-01-071-14/+14
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