iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Cleanup in wreduce	Clifford Wolf	2014-09-14	1	-11/+8
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*	Using pkg-config to find libffi	Clifford Wolf	2014-09-13	1	-2/+2
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*	Fixed simlib $macc model for xilinx xsim	Clifford Wolf	2014-09-08	1	-1/+15
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*	Simplified $fa undef model	Clifford Wolf	2014-09-08	3	-15/+6
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*	Fixes and cleanups for blackbox.v	Clifford Wolf	2014-09-08	2	-70/+73
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*	Added $lcu cell type	Clifford Wolf	2014-09-08	8	-76/+142
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*	Another $clog2 bugfix	Clifford Wolf	2014-09-08	1	-0/+2
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08	8	-6/+165
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*	Trim msb/lsb zero bits from full adder in maccmap	Clifford Wolf	2014-09-08	1	-5/+27
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*	Added "test_cell -const"	Clifford Wolf	2014-09-08	1	-2/+45
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*	Using maccmap for $macc and $mul techmap	Clifford Wolf	2014-09-07	1	-190/+16
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*	Added 'techmap_maccmap' techmap attribute	Clifford Wolf	2014-09-07	1	-19/+53
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*	Added "maccmap" command	Clifford Wolf	2014-09-07	2	-0/+319
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*	Added "test_cell -nosat"	Clifford Wolf	2014-09-07	1	-59/+73
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*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06	4	-4/+5
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*	Added $macc eval model	Clifford Wolf	2014-09-06	1	-0/+22
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*	Added $macc SAT model	Clifford Wolf	2014-09-06	4	-11/+83
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*	Fixed $clog2 (off by one error)	Clifford Wolf	2014-09-06	1	-2/+2
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*	Added $macc simlib model (also use as techmap rule for now)	Clifford Wolf	2014-09-06	2	-0/+172
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*	Fixed assignment of out-of bounds array element	Clifford Wolf	2014-09-06	1	-2/+26
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*	Added $macc cell type	Clifford Wolf	2014-09-06	4	-9/+242
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*	Fixed autotest for non-basename arguments	Clifford Wolf	2014-09-06	1	-0/+3
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-09-06	25	-39/+107
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\| *	Merge pull request #38 from rubund/master	Clifford Wolf	2014-09-06	22	-39/+39
\| \|\ \| \| \| \| \| \|	Corrected spelling mistakes found by lintian
\| \| *	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	22	-39/+39
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\| *	Added tests/various/constmsk_test.ys	Clifford Wolf	2014-09-04	3	-0/+68
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* \|	Added "test_cell -script"	Clifford Wolf	2014-09-06	1	-1/+8
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*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04	1	-9/+4
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	18	-103/+27
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*	Using $pos models for $bu0	Clifford Wolf	2014-09-03	3	-18/+3
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*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03	1	-4/+6
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*	Fixes in $alu SAT- and eval-models	Clifford Wolf	2014-09-03	2	-6/+5
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*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02	1	-3/+6
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*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02	1	-3/+8
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*	Added test_cell -vlog	Clifford Wolf	2014-09-02	1	-2/+79
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*	Create a default selection stack in RTLIL::Design::Design()	Clifford Wolf	2014-09-02	2	-2/+1
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*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02	3	-9/+8
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*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02	1	-1/+89
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*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02	4	-24/+12
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*	Removed yosys-svgviewer	Clifford Wolf	2014-09-02	14	-1121/+18
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*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02	2	-5/+4
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*	Added $alu support to test_cell	Clifford Wolf	2014-09-01	1	-1/+22
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*	Added ConstEval model for $alu cells	Clifford Wolf	2014-09-01	1	-0/+56
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*	Added SAT model for $alu cells	Clifford Wolf	2014-09-01	1	-2/+69
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*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01	1	-2/+3
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*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01	1	-8/+29
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*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01	1	-2/+18
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*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01	1	-3/+4
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*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01	5	-2/+2
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*	Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵	Clifford Wolf	2014-09-01	4	-38/+35
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