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| * Use techmap -share_map in btor scriptsClifford Wolf2014-01-242-2/+2
| * Moved btor scripts to backends/btor/Clifford Wolf2014-01-242-0/+0
| * Restored MakefileClifford Wolf2014-01-241-3/+3
| * Restored IdString::check()Clifford Wolf2014-01-241-1/+1
| * Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btorClifford Wolf2014-01-247-4/+1005
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| * minor change in scriptAhmed Irfan2014-01-241-2/+11
| * Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-223-6/+13
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| * | slice bug correctedAhmed Irfan2014-01-201-1/+1
| * | assert featureAhmed Irfan2014-01-201-9/+40
| * | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-2016-33/+349
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| * | | script addedAhmed Irfan2014-01-182-9/+28
| * | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-180-0/+0
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| | * \ \ Merge branch 'master' of https://github.com/ahmedirfan1983/yosysAhmed Irfan2014-01-180-0/+0
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| | * \ \ \ Merge branch 'master' of https://github.com/cliffordwolf/yosysAhmed Irfan2014-01-1813-12/+451
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| * | \ \ \ \ pmux2muxAhmed Irfan2014-01-187-9/+197
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| * | | | | | verilog default options pullAhmed Irfan2014-01-172-34/+104
| * | | | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-174-7/+119
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| | * | | | | Merge pull request #4 from cliffordwolf/masterAhmed Irfan2014-01-174-7/+119
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| * | | | | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-172-0/+117
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| | * | | | | | Merge pull request #3 from cliffordwolf/masterAhmed Irfan2014-01-172-0/+117
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| * | | | | | | slice error correctedAhmed Irfan2014-01-161-5/+5
| * | | | | | | width issuesAhmed Irfan2014-01-152-65/+88
| * | | | | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-154-15/+60
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| | * | | | | | Merge pull request #2 from cliffordwolf/masterAhmed Irfan2014-01-154-15/+60
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| * | | | | | | | BTOR backendAhmed Irfan2014-01-142-279/+334
| * | | | | | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-147-72/+364
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| | * | | | | | | Merge pull request #1 from cliffordwolf/masterAhmed Irfan2014-01-141-5/+71
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| * | \ \ \ \ \ \ \ splitnet -driver featureAhmed Irfan2014-01-036-45/+343
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| * \ \ \ \ \ \ \ \ \ Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-0343-873/+2070
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| * | | | | | | | | | | makefileAhmed Irfan2014-01-032-3/+3
| * | | | | | | | | | | btorAhmed Irfan2014-01-034-0/+816
* | | | | | | | | | | | Fixed handling of unsized constants in verilog frontendClifford Wolf2014-01-241-2/+2
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* | | | | | | | | | | Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-203-6/+13
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* | | | | | | | | | Added hilomap commandClifford Wolf2014-01-192-0/+130
* | | | | | | | | | Added sat -tempinduc and sat -prove-assertsClifford Wolf2014-01-191-10/+41
* | | | | | | | | | Added $assert support to satgenClifford Wolf2014-01-191-0/+21
* | | | | | | | | | Added $assert cellClifford Wolf2014-01-197-1/+120
* | | | | | | | | | Added Verilog parser support for assertsClifford Wolf2014-01-194-3/+12
* | | | | | | | | | Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-181-10/+12
* | | | | | | | | | Fixed parsing of verilog macros at end of lineClifford Wolf2014-01-181-1/+1
* | | | | | | | | | More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-181-10/+14
* | | | | | | | | | Fixed a type in $mem model in simlib.vClifford Wolf2014-01-181-1/+1
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* | | | | | | | | Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-181-3/+3
* | | | | | | | | Added $bu0 cell to simlib.vClifford Wolf2014-01-181-0/+22
* | | | | | | | | Improved setundef random number generatorClifford Wolf2014-01-181-1/+1
* | | | | | | | | Added setundef commandClifford Wolf2014-01-172-0/+158
* | | | | | | | | Some improvements in log_dump_val_worker() templatesClifford Wolf2014-01-171-1/+6
* | | | | | | | | Added techlibs/common/pmux2mux.vClifford Wolf2014-01-172-1/+26
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* | | | | | | | Added verilog_defaults commandClifford Wolf2014-01-171-0/+66
* | | | | | | | Added support for $adff with undef data inputs to opt_rmdffClifford Wolf2014-01-171-0/+6
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