| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Disable opt_merge for $anyseq and $anyconst | Clifford Wolf | 2017-02-28 | 1 | -0/+3 | |
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| * | Use hex addresses in smtbmc vcd mem traces | Clifford Wolf | 2017-02-28 | 1 | -1/+1 | |
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| * | Add "chformal -assert2assume" and friends | Clifford Wolf | 2017-02-28 | 1 | -0/+44 | |
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| * | Add "chformal" pass | Clifford Wolf | 2017-02-27 | 2 | -0/+239 | |
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| * | Add smtbmc support for memory vcd dumping | Clifford Wolf | 2017-02-26 | 1 | -0/+98 | |
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| * | Fix extra newline bug in write_smt2 | Clifford Wolf | 2017-02-26 | 1 | -1/+1 | |
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| * | Fix bug in smtio unroll code | Clifford Wolf | 2017-02-26 | 1 | -3/+2 | |
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| * | Fix assert checking in "yosys-smtbmc -c --append" | Clifford Wolf | 2017-02-26 | 1 | -1/+1 | |
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| * | Improve (and fix for stbv mode) SMT2 memory API | Clifford Wolf | 2017-02-26 | 3 | -47/+51 | |
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| * | Add support for "yosys-smtbmc -c --append" | Clifford Wolf | 2017-02-25 | 1 | -1/+13 | |
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| * | Update ABC to hg rev 3a95bfa55df7 | Clifford Wolf | 2017-02-25 | 1 | -1/+1 | |
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| * | Merge branch 'klammerj-master' | Clifford Wolf | 2017-02-25 | 1 | -56/+106 | |
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| | * | Improve "write_edif" help message | Clifford Wolf | 2017-02-25 | 1 | -7/+2 | |
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| | * | Move EdifNames out of double-private namespace | Clifford Wolf | 2017-02-25 | 1 | -48/+45 | |
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| | * | Clean up edif code, swap bit indexing of "upto" ports | Clifford Wolf | 2017-02-25 | 1 | -17/+35 | |
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| | * | Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master | Clifford Wolf | 2017-02-25 | 1 | -6/+46 | |
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| | * | Did as you requested, /but/... | Johann Klammer | 2017-02-24 | 2 | -48/+32 | |
| | | | | | | | | | Now the nets are wired in reverse again because the netlister still uses zero-based indices. | |||||
| | * | add options for edif flavors | Johann Klammer | 2017-02-23 | 2 | -7/+63 | |
| | | | | | | | | | | | | | *to force renames on wide ports *to choose array delimiters *to choose up or downwards indices | |||||
| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-02-25 | 1 | -3/+4 | |
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| | * \ | Merge pull request #322 from azonenberg/master | Clifford Wolf | 2017-02-24 | 1 | -3/+4 | |
| | |\ \ | | | | | | | | | Add POUT to GP_COUNTx cells | |||||
| | | * \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-24 | 7 | -37/+113 | |
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| | | * \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-16 | 2 | -3/+9 | |
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| | | * \ \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-14 | 11 | -47/+240 | |
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| | | * \ \ \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-11 | 10 | -58/+273 | |
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| | | * \ \ \ \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-02-08 | 29 | -712/+1257 | |
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| | | * \ \ \ \ \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-01-15 | 3 | -3/+7 | |
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| | | * \ \ \ \ \ \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-01-05 | 5 | -42/+135 | |
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| | | * \ \ \ \ \ \ \ \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2017-01-01 | 4 | -4/+65 | |
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| | | * | | | | | | | | | | greenpak4: Added POUT to GP_COUNTx cells | Andrew Zonenberg | 2017-01-01 | 1 | -3/+4 | |
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| * | | | | | | | | | | | | Add $live and $fair support to AIGER back-end. | Clifford Wolf | 2017-02-25 | 1 | -8/+104 | |
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| * | | | | | | | | | | | | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 14 | -10/+80 | |
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| * | | | | | | | | / / | Add "write_smt2 -stbv" | Clifford Wolf | 2017-02-24 | 3 | -49/+179 | |
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| * | | | | | | | | | | Add SMT2 statebv mode (inactive for now) | Clifford Wolf | 2017-02-24 | 1 | -20/+47 | |
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| * | | | | | | | | | | Merge pull request #320 from joshhead/uninstall-binpath-fix | Clifford Wolf | 2017-02-24 | 1 | -1/+1 | |
| |\ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | Add missing slashes in paths for make uninstall | |||||
| | * | | | | | | | | | Add missing slashes in paths for make uninstall | Josh Headapohl | 2017-02-23 | 1 | -1/+1 | |
| |/ / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Running make uninstall used to fail to remove binaries: rm -vf /usr/local/binyosys /usr/local/binyosys-config #...etc Fix Makefile so that it runs a command like this: rm -vf /usr/local/bin/yosys /usr/local/bin/yosys-config #...etc | |||||
| * | | | | | | | | | Add support for SystemVerilog unique, unique0, and priority case | Clifford Wolf | 2017-02-23 | 2 | -4/+25 | |
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| * | | | | | | | | | Preserve string parameters | Clifford Wolf | 2017-02-23 | 1 | -2/+8 | |
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| * | | | | | | | | | Fix mingw compile issue (2nd attempt) | Clifford Wolf | 2017-02-23 | 1 | -2/+2 | |
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| * | | | | | | | | | Fix mingw compile issue (maybe.. I can't test it) | Clifford Wolf | 2017-02-23 | 1 | -2/+2 | |
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| * | | | | | | | | | Added SystemVerilog support for ++ and -- | Clifford Wolf | 2017-02-23 | 2 | -1/+12 | |
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| * | | | | | | | | | Update ABC to hg rev 8da4dc435b9f | Clifford Wolf | 2017-02-22 | 1 | -1/+1 | |
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| * | | | | | | | | | Add "yosys-smtbmc -S <opt>" | Clifford Wolf | 2017-02-19 | 1 | -7/+18 | |
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| * | | | | | | | | Copy attributes to _TECHMAP_REPLACE_ cells | Clifford Wolf | 2017-02-16 | 1 | -2/+8 | |
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| * | | | | | | | | Fix eval implementation of $_NOR_ | Clifford Wolf | 2017-02-16 | 1 | -1/+1 | |
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| * | | | | | | | Fix incorrect "incompatible re-declaration of wire" error in tasks/functions | Clifford Wolf | 2017-02-14 | 1 | -2/+9 | |
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| * | | | | | | | Add warning about x/z bits left unconnected in EDIF output | Clifford Wolf | 2017-02-14 | 1 | -2/+5 | |
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| * | | | | | | | Fix double-call of log_pop() in synth_greenpak4 | Clifford Wolf | 2017-02-14 | 1 | -2/+0 | |
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| * | | | | | | | Merge pull request #313 from azidar/bugfix-assign-wmask | Clifford Wolf | 2017-02-14 | 3 | -27/+181 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | More progress on Firrtl backend. | |||||
| | * | | | | | | | More progress on Firrtl backend. | Adam Izraelevitz | 2017-02-13 | 3 | -27/+181 | |
| |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design. | |||||
| * | | | | | | | Do not fix port widths on any blackbox instances | Clifford Wolf | 2017-02-13 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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