iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added "nlutmap -assert"	Clifford Wolf	2016-06-09	2	-3/+17
*	Do not run "wreduce" in "prep -ifx"	Clifford Wolf	2016-06-08	1	-2/+3
*	Added "proc_mux -ifx"	Clifford Wolf	2016-06-06	3	-21/+54
*	Added "setundef -init"	Clifford Wolf	2016-06-03	1	-5/+89
*	Fix all undef-muxes in dlatch input cone	Clifford Wolf	2016-06-02	1	-34/+72
*	Avoid creating undef-muxes when inferring latches in proc_dlatch	Clifford Wolf	2016-06-01	1	-0/+44
*	Added opt_expr support for div/mod by power-of-two	Clifford Wolf	2016-05-29	2	-0/+96
*	Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}	Clifford Wolf	2016-05-27	1	-0/+11
*	Fixed access-after-delete bug in mem2reg code	Clifford Wolf	2016-05-27	2	-6/+23
*	fixed typos in error messages	Clifford Wolf	2016-05-27	1	-3/+3
*	Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop	Clifford Wolf	2016-05-27	1	-3/+3
*	Merge pull request #172 from zeldin/deterministic_hierarchy	Clifford Wolf	2016-05-22	1	-3/+3
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\| *	Made the expansion order of hierarchy deterministic	Marcus Comstedt	2016-05-22	1	-3/+3
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*	Some fixes in tests/asicworld/*_tb.v	Clifford Wolf	2016-05-20	4	-50/+41
*	Improvements and fixes in autotest.sh script and test_autotb	Clifford Wolf	2016-05-20	2	-9/+9
*	Merge branch 'master' of https://github.com/Kmanfi/yosys	Clifford Wolf	2016-05-20	2	-11/+18
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\| *	Close opened dump file.	Kaj Tuomi	2016-05-19	1	-0/+1
\| *	Fix for Modelsim transcript line warp issue #164	Kaj Tuomi	2016-05-19	2	-11/+17
* \|	Also escape "=" in spice output	Clifford Wolf	2016-05-20	1	-1/+1
* \|	Small improvements in Verilog front-end docs	Clifford Wolf	2016-05-20	2	-0/+8
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*	Don't sign-extend memory bram initialization data	Clifford Wolf	2016-05-15	1	-1/+1
*	Added missing "#define HASHLIB_H"	Clifford Wolf	2016-05-14	1	-0/+1
*	Minor presentation fixes	Clifford Wolf	2016-05-14	1	-1/+1
*	Updated min GCC requirement to GCC 4.8	Clifford Wolf	2016-05-11	2	-14/+14
*	Added manual download link to README	Clifford Wolf	2016-05-09	1	-0/+4
*	Include <cmath> in yosys.h	Clifford Wolf	2016-05-08	2	-9/+1
*	Merge pull request #162 from azonenberg/master	Clifford Wolf	2016-05-08	1	-2/+33
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\| *	Added GP_DELAY cell	Andrew Zonenberg	2016-05-07	1	-0/+29
\| *	Fixed typo in port name	Andrew Zonenberg	2016-05-07	1	-1/+1
\| *	Fixed extra semicolon	Andrew Zonenberg	2016-05-07	1	-1/+1
\| *	Fixed typo in parameter name	Andrew Zonenberg	2016-05-07	1	-1/+1
\| *	Added simulation timescale declaration	Andrew Zonenberg	2016-05-07	1	-0/+2
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*	Fixes for MXE build	Clifford Wolf	2016-05-07	3	-10/+10
*	Added support for "keep" attribute to shregmap	Clifford Wolf	2016-05-07	1	-2/+2
*	Added synth_ice40 support for latches via logic loops	Clifford Wolf	2016-05-06	3	-0/+13
*	Added "write_blif -noalias"	Clifford Wolf	2016-05-06	1	-6/+26
*	Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"	Clifford Wolf	2016-05-06	1	-3/+15
*	Fixed preservation of important attributes in techmap	Clifford Wolf	2016-05-06	1	-4/+32
*	Merge pull request #159 from azonenberg/master	Clifford Wolf	2016-05-05	5	-24/+7
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\| *	Changed order of passes for better handling of INIT attributes on "output reg...	Andrew Zonenberg	2016-05-04	1	-2/+2
\| *	Changed port names in greenpak shregmap	Andrew Zonenberg	2016-05-04	1	-1/+1
\| *	Renamed module parameter	Andrew Zonenberg	2016-05-04	1	-4/+4
\| *	Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cell...	Andrew Zonenberg	2016-05-04	3	-18/+1
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*	Added tristate buffer support to iopadmap	Clifford Wolf	2016-05-04	1	-4/+161
*	Merge pull request #157 from azonenberg/master	Clifford Wolf	2016-05-04	5	-0/+52
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\| *	Fixed incorrect signal naming in GP_IOBUF	Andrew Zonenberg	2016-05-04	1	-2/+2
\| *	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-05-04	1	-0/+1
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* \|	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2016-05-04	1	-0/+11
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* \| \|	Fixed iopadmap attribute handling	Clifford Wolf	2016-05-04	1	-0/+1
\| \| *	Added tri-state I/O extraction for GreenPak	Andrew Zonenberg	2016-05-03	5	-2/+29