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* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-05-041-0/+11
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* | | Fixed iopadmap attribute handlingClifford Wolf2016-05-041-0/+1
| | * Added tri-state I/O extraction for GreenPakAndrew Zonenberg2016-05-035-2/+29
| | * Added GreenPak I/O buffer cellsAndrew Zonenberg2016-05-031-0/+17
| | * Added comment to clarify GP_ABUF cellAndrew Zonenberg2016-05-021-0/+2
| | * Added GP_ABUF cellAndrew Zonenberg2016-05-021-0/+6
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| * Merge pull request #154 from azonenberg/masterClifford Wolf2016-05-021-0/+11
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| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-05-011-1/+1
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* | Improved TCL_VERSION detection so it does not read .tclshrcClifford Wolf2016-04-291-1/+1
| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-291-0/+30
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* | Added "qwp -v"Clifford Wolf2016-04-281-0/+30
| * Added GP_PGA cellAndrew Zonenberg2016-04-271-0/+11
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* Connections between inputs and inouts are driven by the inputClifford Wolf2016-04-261-0/+3
* Fixed test_autotb for modules with many cell portsClifford Wolf2016-04-251-3/+6
* Fixed proc_mux performance bugClifford Wolf2016-04-251-0/+3
* Merge pull request #150 from azonenberg/masterClifford Wolf2016-04-251-0/+13
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| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-246-72/+163
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* | Fixed performance bug in proc_dlatchClifford Wolf2016-04-241-2/+61
* | Added "yosys -D ALL"Clifford Wolf2016-04-243-6/+22
* | Added "prep -flatten" and "synth -flatten"Clifford Wolf2016-04-242-7/+36
* | Converted "prep" to ScriptPassClifford Wolf2016-04-242-60/+47
| * Removed VIN_BUF_ENAndrew Zonenberg2016-04-241-1/+0
| * Renamed VOUT to OUT on GP_ACMP cellAndrew Zonenberg2016-04-231-1/+3
| * Added GP_ACMP cellAndrew Zonenberg2016-04-231-0/+12
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* Improvements in greenpak4 shreg mappingClifford Wolf2016-04-231-16/+35
* Run clean after splitnets in synth_greenpak4Clifford Wolf2016-04-231-1/+1
* Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-231-0/+1
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| * Added "shregmap -zinit" for greenpak4 techClifford Wolf2016-04-231-0/+1
* | Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-232-111/+72
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| * Merge https://github.com/azonenberg/yosysClifford Wolf2016-04-231-1/+7
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| * | Added "shregmap" to synth_greenpak4Clifford Wolf2016-04-231-0/+1
| * | Converted synth_greenpak4 to ScriptPassClifford Wolf2016-04-232-111/+71
* | | Fixed typo in help textAndrew Zonenberg2016-04-221-1/+1
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* | Fixed typoAndrew Zonenberg2016-04-221-1/+1
* | Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-22118-202/+497
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| * Added "shregmap -tech greenpak4"Clifford Wolf2016-04-221-6/+97
| * Added support for "active high" and "active low" latches in BLIF front-endClifford Wolf2016-04-221-0/+4
| * Added support for "active high" and "active low" latches in BLIF back-endClifford Wolf2016-04-221-0/+12
| * More flexible handling of initialization valuesClifford Wolf2016-04-221-7/+22
| * Added "yosys -D" featureClifford Wolf2016-04-21113-145/+172
| * Fixed performance bug in "share" passClifford Wolf2016-04-211-2/+51
| * Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-215-8/+37
| * Improvements in opt_exprClifford Wolf2016-04-211-12/+62
| * Bugfix and improvements in memory_shareClifford Wolf2016-04-212-22/+40
* | Added GP_VREF cellAndrew Zonenberg2016-04-201-0/+6
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* Merge pull request #149 from azonenberg/masterClifford Wolf2016-04-191-96/+156
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| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-181-5/+107
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* | Added "shregmap -params"Clifford Wolf2016-04-181-4/+43
* | Added "shregmap -zinit" and "shregmap -init"Clifford Wolf2016-04-181-2/+65
| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-171-30/+140
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