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verilog: Add location info for generate constructs
David Shah
2020-04-01
1
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+6
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Merge pull request #1852 from boqwxp/cleanup_synth_ice40
Eddie Hung
2020-04-01
1
-4
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+4
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Fix indentation in `techlibs/ice40/synth_ice40.cc`.
Alberto Gonzalez
2020-04-01
1
-4
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+4
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Merge pull request #1849 from boqwxp/cleanup_kernel_yosys
Eddie Hung
2020-04-01
1
-14
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+13
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Clean up pseudo-private member usage in `kernel/yosys.cc`.
Alberto Gonzalez
2020-04-01
1
-14
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+13
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Merge pull request #1850 from boqwxp/cleanup_backends
Eddie Hung
2020-04-01
7
-103
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+84
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Update `RTLIL::id2cstr()` usage to `log_id`.
Alberto Gonzalez
2020-04-01
1
-2
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+2
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Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`.
Alberto Gonzalez
2020-04-01
1
-22
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+19
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Clean up pseudo-private member usage in `backends/blif/blif.cc`.
Alberto Gonzalez
2020-04-01
1
-15
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+11
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Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`.
Alberto Gonzalez
2020-04-01
1
-22
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+19
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Clean up pseudo-private member usage in `backends/spice/spice.cc`.
Alberto Gonzalez
2020-04-01
1
-13
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+9
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Clean up pseudo-private member usage in `backends/edif/edif.cc`.
Alberto Gonzalez
2020-04-01
1
-23
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+18
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Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`.
Alberto Gonzalez
2020-04-01
1
-6
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+6
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Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
Claire Wolf
2020-04-01
2
-1
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+13
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ast: simplify to fully populate dynamic slicing case transformation
Eddie Hung
2020-03-31
1
-1
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+1
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Add dynamic slicing Verilog testcase
Eddie Hung
2020-03-31
1
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+12
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Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
Eddie Hung
2020-03-31
3
-132
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+194
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opt_merge: unordered_map -> dict as per @cliffordwolf review
Eddie Hung
2020-03-16
1
-1
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+1
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opt_merge: speedup
Eddie Hung
2020-03-16
3
-132
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+194
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Merge pull request #1783 from boqwxp/astcc_cleanup
Eddie Hung
2020-03-30
1
-13
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+20
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Add explanatory comment about inefficient wire removal and remove superfluous...
Alberto Gonzalez
2020-03-30
1
-4
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+8
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Revert over-aggressive change to a more modest cleanup.
Alberto Gonzalez
2020-03-27
1
-2
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+3
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Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
Alberto Gonzalez
2020-03-19
1
-11
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+13
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Merge pull request #1835 from boqwxp/cleanup_sat_expose
Eddie Hung
2020-03-30
1
-85
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+66
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Remove unused function parameter.
Alberto Gonzalez
2020-03-30
1
-2
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+2
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Simplify iterating over selected modules or cells.
Alberto Gonzalez
2020-03-30
1
-16
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+4
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Clean up more in `passes/sat/expose.cc`.
Alberto Gonzalez
2020-03-30
1
-64
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+59
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Clean up pseudo-private member usage in `passes/sat/expose.cc`.
Alberto Gonzalez
2020-03-28
1
-11
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+9
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Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design
Eddie Hung
2020-03-30
1
-31
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+33
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Replace `RTLIL::id2cstr()` with `log_id()`.
Alberto Gonzalez
2020-03-30
1
-1
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+1
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Clean up pseudo-private member usage in `passes/cmds/design.cc`.
Alberto Gonzalez
2020-03-28
1
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+33
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Merge pull request #1786 from boqwxp/hierarchycc_cleanup
Eddie Hung
2020-03-30
1
-69
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+63
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Fix double deletion in `passes/hierarchy/hierarchy.cc`.
Alberto Gonzalez
2020-03-30
1
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+0
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Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
Alberto Gonzalez
2020-03-19
1
-68
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+63
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Merge pull request #1831 from boqwxp/cleanup_sat_eval
Eddie Hung
2020-03-30
1
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+44
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Further clean up `passes/sat/eval.cc`.
Alberto Gonzalez
2020-03-30
1
-16
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+15
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Clean up pseudo-private member usage in `passes/sat/eval.cc`.
Alberto Gonzalez
2020-03-28
1
-35
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+34
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Merge pull request #1833 from boqwxp/cleanup_sat_freduce
Eddie Hung
2020-03-30
1
-15
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+13
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Further clean up `passes/sat/freduce.cc`.
Alberto Gonzalez
2020-03-30
1
-3
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+2
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Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
Alberto Gonzalez
2020-03-28
1
-13
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+12
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Merge pull request #1811 from PeterCrozier/typedef_scope
N. Engelhardt
2020-03-30
6
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+88
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Inline productions to follow house style.
Peter Crozier
2020-03-27
1
-33
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+29
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Error duplicate declarations of a typedef name in the same scope.
Peter Crozier
2020-03-24
2
-3
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+11
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Support module/package/interface/block scope for typedef names.
Peter Crozier
2020-03-23
6
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+63
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Merge pull request #1778 from rswarbrick/sv-defines
N. Engelhardt
2020-03-30
11
-151
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+636
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Add support for SystemVerilog-style `define to Verilog frontend
Rupert Swarbrick
2020-03-27
11
-151
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+636
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Explicit include of csignal
Miodrag Milanovic
2020-03-28
1
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+1
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windows - there are no stopping signals
Miodrag Milanovic
2020-03-28
1
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+1
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Merge pull request #1607 from whitequark/simplify-simplify-meminit
Claire Wolf
2020-03-27
1
-63
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+82
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ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
whitequark
2020-02-07
1
-65
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+84
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