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* Merge branch 'master' of https://github.com/Kmanfi/yosysClifford Wolf2016-05-202-11/+18
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| * Close opened dump file.Kaj Tuomi2016-05-191-0/+1
| * Fix for Modelsim transcript line warp issue #164Kaj Tuomi2016-05-192-11/+17
* | Also escape "=" in spice outputClifford Wolf2016-05-201-1/+1
* | Small improvements in Verilog front-end docsClifford Wolf2016-05-202-0/+8
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* Don't sign-extend memory bram initialization dataClifford Wolf2016-05-151-1/+1
* Added missing "#define HASHLIB_H"Clifford Wolf2016-05-141-0/+1
* Minor presentation fixesClifford Wolf2016-05-141-1/+1
* Updated min GCC requirement to GCC 4.8Clifford Wolf2016-05-112-14/+14
* Added manual download link to READMEClifford Wolf2016-05-091-0/+4
* Include <cmath> in yosys.hClifford Wolf2016-05-082-9/+1
* Merge pull request #162 from azonenberg/masterClifford Wolf2016-05-081-2/+33
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| * Added GP_DELAY cellAndrew Zonenberg2016-05-071-0/+29
| * Fixed typo in port nameAndrew Zonenberg2016-05-071-1/+1
| * Fixed extra semicolonAndrew Zonenberg2016-05-071-1/+1
| * Fixed typo in parameter nameAndrew Zonenberg2016-05-071-1/+1
| * Added simulation timescale declarationAndrew Zonenberg2016-05-071-0/+2
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* Fixes for MXE buildClifford Wolf2016-05-073-10/+10
* Added support for "keep" attribute to shregmapClifford Wolf2016-05-071-2/+2
* Added synth_ice40 support for latches via logic loopsClifford Wolf2016-05-063-0/+13
* Added "write_blif -noalias"Clifford Wolf2016-05-061-6/+26
* Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"Clifford Wolf2016-05-061-3/+15
* Fixed preservation of important attributes in techmapClifford Wolf2016-05-061-4/+32
* Merge pull request #159 from azonenberg/masterClifford Wolf2016-05-055-24/+7
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| * Changed order of passes for better handling of INIT attributes on "output reg...Andrew Zonenberg2016-05-041-2/+2
| * Changed port names in greenpak shregmapAndrew Zonenberg2016-05-041-1/+1
| * Renamed module parameterAndrew Zonenberg2016-05-041-4/+4
| * Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cell...Andrew Zonenberg2016-05-043-18/+1
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* Added tristate buffer support to iopadmapClifford Wolf2016-05-041-4/+161
* Merge pull request #157 from azonenberg/masterClifford Wolf2016-05-045-0/+52
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| * Fixed incorrect signal naming in GP_IOBUFAndrew Zonenberg2016-05-041-2/+2
| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-05-041-0/+1
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* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-05-041-0/+11
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* | | Fixed iopadmap attribute handlingClifford Wolf2016-05-041-0/+1
| | * Added tri-state I/O extraction for GreenPakAndrew Zonenberg2016-05-035-2/+29
| | * Added GreenPak I/O buffer cellsAndrew Zonenberg2016-05-031-0/+17
| | * Added comment to clarify GP_ABUF cellAndrew Zonenberg2016-05-021-0/+2
| | * Added GP_ABUF cellAndrew Zonenberg2016-05-021-0/+6
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| * Merge pull request #154 from azonenberg/masterClifford Wolf2016-05-021-0/+11
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| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-05-011-1/+1
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* | Improved TCL_VERSION detection so it does not read .tclshrcClifford Wolf2016-04-291-1/+1
| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-291-0/+30
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* | Added "qwp -v"Clifford Wolf2016-04-281-0/+30
| * Added GP_PGA cellAndrew Zonenberg2016-04-271-0/+11
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* Connections between inputs and inouts are driven by the inputClifford Wolf2016-04-261-0/+3
* Fixed test_autotb for modules with many cell portsClifford Wolf2016-04-251-3/+6
* Fixed proc_mux performance bugClifford Wolf2016-04-251-0/+3
* Merge pull request #150 from azonenberg/masterClifford Wolf2016-04-251-0/+13
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| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-246-72/+163
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* | Fixed performance bug in proc_dlatchClifford Wolf2016-04-241-2/+61
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