iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Bugfix in Xilinx LUT mapping	Clifford Wolf	2015-10-30	1	-1/+1
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*	Improved SigMap performance	Clifford Wolf	2015-10-28	3	-5/+16
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*	Improvements in new SigMap	Clifford Wolf	2015-10-28	1	-5/+16
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*	Use mfp<> in equiv_mark	Clifford Wolf	2015-10-27	1	-28/+4
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*	Removed old SigMap implementation	Clifford Wolf	2015-10-27	1	-224/+0
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*	Added hashlib::mfp and new SigMap	Clifford Wolf	2015-10-27	3	-0/+185
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*	Improvements in equiv_struct	Clifford Wolf	2015-10-25	1	-17/+62
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*	Major refactoring of equiv_struct	Clifford Wolf	2015-10-25	2	-93/+170
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	39	-161/+168
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*	Added "equiv_add -cell"	Clifford Wolf	2015-10-25	2	-34/+95
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*	equiv_struct now creates equiv_merged attributes	Clifford Wolf	2015-10-25	1	-0/+3
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*	Improvements in equiv_struct	Clifford Wolf	2015-10-24	1	-1/+22
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*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24	8	-34/+34
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*	improvement in "stat"	Clifford Wolf	2015-10-24	1	-1/+1
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*	Fixed driver conflict handling (various cmds)	Clifford Wolf	2015-10-24	1	-3/+12
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*	equiv_purge bugfix, using SigChunk in Yosys namespace	Clifford Wolf	2015-10-24	5	-5/+8
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*	Fixed handling of driver-driver conflicts in wreduce	Clifford Wolf	2015-10-24	3	-9/+42
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*	Added equiv_mark command	Clifford Wolf	2015-10-23	3	-1/+265
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*	Disabled "Skipping blackbox module" msg in show command	Clifford Wolf	2015-10-23	1	-1/+1
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*	Added support for ":" as comment symbol after ;-parsing	Clifford Wolf	2015-10-23	1	-1/+1
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*	Also merge $equiv cells in equiv_struct	Clifford Wolf	2015-10-23	1	-0/+1
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*	Improvements in equiv_struct	Clifford Wolf	2015-10-23	1	-11/+18
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*	Added equiv_purge	Clifford Wolf	2015-10-22	2	-0/+210
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*	Added equiv_struct command	Clifford Wolf	2015-10-21	2	-0/+188
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*	Improved inout handling in equiv_make	Clifford Wolf	2015-10-21	1	-1/+1
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*	Progress on cell help messages	Clifford Wolf	2015-10-20	1	-18/+114
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*	Progress on cell help messages	Clifford Wolf	2015-10-17	3	-54/+107
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*	Progress in yosys-smtbmc	Clifford Wolf	2015-10-15	1	-4/+10
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*	Fixed bug in verilog parser	Clifford Wolf	2015-10-15	1	-1/+1
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*	Improvements in yosys-smtbmc	Clifford Wolf	2015-10-15	3	-2/+9
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*	Bugfixes in handling of "keep" attribute on wires	Clifford Wolf	2015-10-15	2	-2/+8
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*	More "yosys-smtbmc -c" fixes	Clifford Wolf	2015-10-14	2	-9/+30
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*	Fixed yosys-smtbmc -c	Clifford Wolf	2015-10-14	1	-2/+2
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*	Added "prep" command	Clifford Wolf	2015-10-14	2	-0/+157
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*	Added more cell descriptions	Clifford Wolf	2015-10-14	1	-0/+85
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*	Added first help messages for cell types	Clifford Wolf	2015-10-14	6	-6/+336
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*	Added yosys-smtbmc copyright	Clifford Wolf	2015-10-14	3	-1/+36
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*	Improvements in yosys-smtbmc	Clifford Wolf	2015-10-14	3	-21/+38
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*	Added yosys-smtbmc	Clifford Wolf	2015-10-14	2	-1/+20
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*	Implemented smtbmc.py -i	Clifford Wolf	2015-10-14	1	-25/+60
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*	Added smtbmc.py	Clifford Wolf	2015-10-13	4	-0/+409
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*	Added write_smt2 -wires	Clifford Wolf	2015-10-13	1	-7/+15
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*	Added examples/ top-level directory	Clifford Wolf	2015-10-13	17	-4/+7
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*	SystemVerilog also has assume(), added implicit -D FORMAL	Clifford Wolf	2015-10-13	3	-4/+5
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*	Merge branch 'master' of https://github.com/rubund/yosys	Clifford Wolf	2015-10-13	1	-18/+18
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\| *	Use DESTDIR as defined in ↵	Ruben Undheim	2015-10-11	1	-13/+13
\| \| \| \| \| \| \| \| \| \| \| \|	https://www.gnu.org/prep/standards/html_node/DESTDIR.html This is needed for painless packaging of yosys
\| *	Use LDFLAGS, CXXFLAGS and CPPFLAGS from the environment when building	Ruben Undheim	2015-10-11	1	-7/+7
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* \|	Fixed "flatten" for unconnected inout ports	Clifford Wolf	2015-10-13	1	-1/+1
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*	Added support for "parameter" and "localparam" in global context	Clifford Wolf	2015-10-07	1	-0/+2
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*	Fixed complexity of assigning to vectors in constant functions	Clifford Wolf	2015-10-01	1	-0/+3
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