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Age
Files
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*
Add {get,set}_src_attribute() methods on RTLIL::AttrObject
Clifford Wolf
2017-08-30
2
-0
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+20
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Merge branch 'azonenberg-recover-reduce'
Clifford Wolf
2017-08-28
2
-0
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+240
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Rename recover_reduce to extract_reduce, fix args handling
Clifford Wolf
2017-08-28
2
-8
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+25
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Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azo...
Clifford Wolf
2017-08-28
2
-0
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+223
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recover_reduce: Update documentation
Robert Ou
2017-08-27
1
-8
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+11
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recover_reduce: Reindent using tabs
Robert Ou
2017-08-27
1
-190
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+190
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recover_reduce: Rename recover_reduce_core to recover_reduce
Robert Ou
2017-08-27
3
-101
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+0
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recover_reduce: Add driver script for the $reduce_* recover feature
Robert Ou
2017-08-27
2
-0
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+101
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recover_reduce_core: Finish implementing the core function
Robert Ou
2017-08-27
1
-0
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+110
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recover_reduce_core: Initial commit
Robert Ou
2017-08-27
2
-0
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+110
*
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Further improve extract_fa pass
Clifford Wolf
2017-08-28
1
-1
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+42
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Merge pull request #392 from azonenberg/greenpak-portfixes
Clifford Wolf
2017-08-28
1
-2
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+2
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Fixed bug causing GP_SPI model to not synthesize
Andrew Zonenberg
2017-08-27
1
-2
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+2
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Don't track , ... contradictions through x/z-bits
Clifford Wolf
2017-08-25
1
-1
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+4
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Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr
Clifford Wolf
2017-08-25
1
-0
/
+72
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Merge branch 'extract_fa'
Clifford Wolf
2017-08-25
2
-0
/
+502
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Further improve extract_fa (seems to be fully functional now)
Clifford Wolf
2017-08-25
1
-10
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+226
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Rename "adders" to "extract_fa"
Clifford Wolf
2017-08-25
2
-28
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+16
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Towards more generic "adder" function extractor
Clifford Wolf
2017-08-23
1
-202
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+53
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Add experimental adders pass
Clifford Wolf
2017-08-22
2
-0
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+447
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Fix bug in write_smt2 (export logic driving hierarchical cells before exporti...
Clifford Wolf
2017-08-25
1
-34
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+34
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Add hashlib support for hashing of pools
Clifford Wolf
2017-08-22
1
-0
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+7
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Add consteval support for $_ANDNOT_ and $_ORNOT_
Clifford Wolf
2017-08-22
1
-0
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+4
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Remove some dead code from fsm_map
Clifford Wolf
2017-08-21
1
-3
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+0
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Rename "singleton" pass to "uniquify"
Clifford Wolf
2017-08-20
3
-21
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+22
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More intuitive handling of "cd .." for singleton modules
Clifford Wolf
2017-08-19
1
-2
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+38
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Add "sim -zinit -rstlen"
Clifford Wolf
2017-08-18
1
-1
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+53
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Merge branch 'sim'
Clifford Wolf
2017-08-18
4
-0
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+848
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Add "sim" support for memories
Clifford Wolf
2017-08-18
1
-2
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+136
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Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()
Clifford Wolf
2017-08-18
2
-0
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+37
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Add support for assert/assume/cover to "sim" command
Clifford Wolf
2017-08-18
1
-4
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+47
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Add writeback mode to "sim" command
Clifford Wolf
2017-08-17
1
-0
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+44
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Improve "sim" command
Clifford Wolf
2017-08-17
1
-54
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+272
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Add "sim" command skeleton
Clifford Wolf
2017-08-16
2
-0
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+372
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Merge pull request #386 from azonenberg/gpak-counters
Clifford Wolf
2017-08-16
1
-73
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+82
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Fixed more issues with GreenPAK counter sim models
Andrew Zonenberg
2017-08-15
1
-19
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+23
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Updated PGEN model to have level triggered reset (matches actual hardware beh...
Andrew Zonenberg
2017-08-15
1
-4
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+4
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Fixed bug in GP_COUNTx model
Andrew Zonenberg
2017-08-15
1
-7
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+12
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Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high
Andrew Zonenberg
2017-08-15
1
-47
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+47
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Merge branch 'azonenberg-rmports'
Clifford Wolf
2017-08-15
2
-0
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+188
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Mostly coding style related fixes in rmports pass
Clifford Wolf
2017-08-15
1
-30
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+33
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Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg...
Clifford Wolf
2017-08-15
2
-0
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+185
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rmports: Now remove ports from cell instances if we optimized them out of tha...
Andrew Zonenberg
2017-08-14
1
-2
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+35
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ProcessModule is no longer virtual (why was it in the first place?)
Andrew Zonenberg
2017-08-14
1
-1
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+1
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rmports now works on all modules in the design, not just the top.
Andrew Zonenberg
2017-08-14
1
-4
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+7
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Updated Makefile to reflect opt_rmports being renamed to rmports
Andrew Zonenberg
2017-08-14
1
-1
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+1
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Renamed opt_rmports pass to rmports
Andrew Zonenberg
2017-08-14
1
-5
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+5
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Improved handling of constant connections in opt_rmports
Andrew Zonenberg
2017-08-14
1
-0
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+2
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Fixed handling of cell ports that aren't wires
Andrew Zonenberg
2017-08-14
1
-0
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+3
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opt_rmports: Fixed incorrect handling of multi-bit nets
Andrew Zonenberg
2017-08-14
1
-12
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+27
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