| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | | | | Remove unused output | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
| | | * | | | | Fix tribuf test | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
| | | * | | | | Fix comments | Eddie Hung | 2019-08-22 | 8 | -10/+11 | |
| | | * | | | | Remove tech independent synthesis | Eddie Hung | 2019-08-22 | 9 | -16/+20 | |
| | | * | | | | Remove dffe instantation | Eddie Hung | 2019-08-22 | 1 | -7/+0 | |
| | | * | | | | Move $dffe to dffs.{v,ys} | Eddie Hung | 2019-08-22 | 4 | -18/+41 | |
| | | * | | | | Make multiplier wider, do not do tech independent synth | Eddie Hung | 2019-08-22 | 2 | -8/+6 | |
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| | * | | | | Fix all comments from PR | SergeyDegtyar | 2019-08-21 | 20 | -160/+465 | |
| | * | | | | Add temp directory | SergeyDegtyar | 2019-08-21 | 1 | -0/+1 | |
| | * | | | | Fix tests; Remove simulation; | SergeyDegtyar | 2019-08-20 | 26 | -519/+33 | |
| | * | | | | Add new tests for ice40 architecture | SergeyDegtyar | 2019-08-20 | 28 | -0/+901 | |
| * | | | | | Merge pull request #1321 from YosysHQ/eddie/xilinx_srl | Eddie Hung | 2019-08-30 | 13 | -224/+816 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-30 | 18 | -139/+264 | |
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| | * | | | | | | Cleanup | Eddie Hung | 2019-08-28 | 1 | -4/+0 | |
| | * | | | | | | Account for D port being a constant | Eddie Hung | 2019-08-28 | 1 | -4/+4 | |
| | * | | | | | | No need to replace Q of slice since $shiftx is autoremove-d | Eddie Hung | 2019-08-28 | 1 | -1/+0 | |
| | * | | | | | | More cleanup | Eddie Hung | 2019-08-28 | 1 | -12/+14 | |
| | * | | | | | | More cleanup | Eddie Hung | 2019-08-28 | 1 | -9/+6 | |
| | * | | | | | | Do not use default_params dict, hardcode default values, cleanup | Eddie Hung | 2019-08-28 | 2 | -25/+21 | |
| | * | | | | | | Add .gitignore | Eddie Hung | 2019-08-28 | 1 | -0/+3 | |
| | * | | | | | | Use test_pmgen for xilinx_srl | Eddie Hung | 2019-08-28 | 1 | -0/+57 | |
| | * | | | | | | Always generate if no match | Eddie Hung | 2019-08-28 | 1 | -1/+1 | |
| | * | | | | | | Rename test_pmgen arg xilinx_srl.{fixed,variable} | Eddie Hung | 2019-08-28 | 1 | -2/+2 | |
| | * | | | | | | Do not simplemap for variable test | Eddie Hung | 2019-08-28 | 1 | -2/+2 | |
| | * | | | | | | Add xilinx_srl test | Eddie Hung | 2019-08-28 | 3 | -0/+127 | |
| | * | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 27 | -347/+1438 | |
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| | * | | | | | | | Missing close bracket | Eddie Hung | 2019-08-26 | 1 | -1/+1 | |
| | * | | | | | | | Revert "In sat: 'x' in init attr should not override constant" | Eddie Hung | 2019-08-26 | 3 | -7/+1 | |
| | * | | | | | | | Remove leftover header | Eddie Hung | 2019-08-26 | 1 | -1/+0 | |
| | * | | | | | | | Improve xilinx_srl.fixed generate, add .variable generate | Eddie Hung | 2019-08-26 | 1 | -26/+75 | |
| | * | | | | | | | Account for maxsubcnt overflowing | Eddie Hung | 2019-08-26 | 1 | -1/+1 | |
| | * | | | | | | | Add xilinx_srl_pm.variable to test_pmgen | Eddie Hung | 2019-08-26 | 1 | -0/+2 | |
| | * | | | | | | | Populate generate for xilinx_srl.fixed pattern | Eddie Hung | 2019-08-26 | 1 | -22/+54 | |
| | * | | | | | | | Add xilinx_srl_fixed, fix typos | Eddie Hung | 2019-08-26 | 1 | -2/+6 | |
| | * | | | | | | | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 4 | -28/+125 | |
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| | * | | | | | | | | Create new $__XILINX_SHREG_ cell for variable length too | Eddie Hung | 2019-08-23 | 1 | -31/+30 | |
| | * | | | | | | | | Do not allow Q of last cell of variable length SRL to be (* keep *) | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
| | * | | | | | | | | Also add first.Q to chain_bits since variable length | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
| | * | | | | | | | | Do not enforce !EN_POLARITY on $dffe | Eddie Hung | 2019-08-23 | 1 | -2/+0 | |
| | * | | | | | | | | Create new cell for fixed length SRL | Eddie Hung | 2019-08-23 | 1 | -14/+22 | |
| | * | | | | | | | | Cleanup FDRE matching | Eddie Hung | 2019-08-23 | 1 | -45/+19 | |
| | * | | | | | | | | Oops don't need a finally block | Eddie Hung | 2019-08-23 | 1 | -5/+0 | |
| | * | | | | | | | | Keep track of bits in variable length chain, to check for taps | Eddie Hung | 2019-08-23 | 1 | -0/+12 | |
| | * | | | | | | | | Don't forget $dff has no EN | Eddie Hung | 2019-08-23 | 1 | -2/+4 | |
| | * | | | | | | | | Same for variable length | Eddie Hung | 2019-08-23 | 1 | -2/+10 | |
| | * | | | | | | | | Filter on en_port for fixed length | Eddie Hung | 2019-08-23 | 1 | -4/+24 | |
| | * | | | | | | | | Check clock is consistent | Eddie Hung | 2019-08-23 | 1 | -5/+25 | |
| | * | | | | | | | | Fix last_cell.D | Eddie Hung | 2019-08-23 | 1 | -2/+1 | |
| | * | | | | | | | | Revert "Add a unique argument to pmgen's nusers()" | Eddie Hung | 2019-08-23 | 1 | -8/+4 | |
| | * | | | | | | | | Revert "Fix polarity" | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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