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* Improve stack rlimit code in smtio.pyClifford Wolf2018-11-061-8/+8
* Allow square brackets in liberty identifiersClifford Wolf2018-11-052-3/+4
* Merge pull request #691 from arjenroodselaar/stacksizeClifford Wolf2018-11-051-1/+6
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| * Use conservative stack size for SMT2 on MacOSArjen Roodselaar2018-11-041-1/+6
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* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
* Add proper error message for when smtbmc "append" failsClifford Wolf2018-11-041-2/+10
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
* Merge pull request #687 from trcwm/masterClifford Wolf2018-11-042-4/+10
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| * Liberty file newline handling is more relaxed. More descriptive error messageNiels Moseley2018-11-031-4/+7
| * Report an error when a liberty file contains pin references that reference no...Niels Moseley2018-11-031-0/+3
* | Merge pull request #688 from ZipCPU/rosenfellClifford Wolf2018-11-041-2/+8
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| * Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
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* Do not generate "reg assigned in a continuous assignment" warnings for "rand ...Clifford Wolf2018-11-011-2/+15
* Add support for signed $shift/$shiftx in smt2 back-endClifford Wolf2018-11-011-1/+3
* Merge branch 'igloo2'Clifford Wolf2018-10-315-0/+377
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| * Fix sf2 LUT interfaceClifford Wolf2018-10-312-12/+12
| * Basic SmartFusion2 and IGLOO2 synthesis supportClifford Wolf2018-10-315-0/+377
* | Merge pull request #680 from jburgess777/fix-empty-string-back-assertClifford Wolf2018-10-301-1/+1
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| * Avoid assert when label is an empty stringJon Burgess2018-10-281-1/+1
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* Merge pull request #678 from whentze/masterClifford Wolf2018-10-251-2/+2
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| * fix unhandled std::out_of_range when calling yosys with 3-character argumentwhentze2018-10-221-2/+2
* | Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* | Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-2514-14/+78
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| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-2514-14/+78
* | | Merge pull request #677 from daveshah1/ecp5_dspClifford Wolf2018-10-233-1/+97
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| * | ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
| * | ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
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* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
* | Merge pull request #674 from rubund/feature/svinterface_at_topClifford Wolf2018-10-2011-70/+599
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| * Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-204-136/+113
| * Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-209-10/+561
| * Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #673 from daveshah1/ecp5_improveClifford Wolf2018-10-194-6/+17
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| * ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
| * ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
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* Merge pull request #672 from daveshah1/fix_bramClifford Wolf2018-10-191-0/+1
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| * memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
* | Merge pull request #671 from rafaeltp/masterClifford Wolf2018-10-191-2/+3
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| * | adding offset info to memoriesrafaeltp2018-10-181-1/+1
| * | adding offset info to memoriesrafaeltp2018-10-181-2/+3
* | | Merge pull request #670 from rubund/feature/basic_svinterface_testClifford Wolf2018-10-196-9/+248
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| * | Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-186-9/+248
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* | Update ABC to git rev 14d985aClifford Wolf2018-10-181-1/+1
* | Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-1811-21/+649
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| * | Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
| * | Documentation improvements etc.Ruben Undheim2018-10-135-38/+77
| * | Fix build error with clangRuben Undheim2018-10-121-1/+1
| * | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-128-14/+121
| * | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-1210-21/+501
* | | Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
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