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* minor change in scriptAhmed Irfan2014-01-241-2/+11
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-223-6/+13
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| * Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-203-6/+13
* | slice bug correctedAhmed Irfan2014-01-201-1/+1
* | assert featureAhmed Irfan2014-01-201-9/+40
* | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-2016-33/+349
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| * Added hilomap commandClifford Wolf2014-01-192-0/+130
| * Added sat -tempinduc and sat -prove-assertsClifford Wolf2014-01-191-10/+41
| * Added $assert support to satgenClifford Wolf2014-01-191-0/+21
| * Added $assert cellClifford Wolf2014-01-197-1/+120
| * Added Verilog parser support for assertsClifford Wolf2014-01-194-3/+12
| * Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-181-10/+12
| * Fixed parsing of verilog macros at end of lineClifford Wolf2014-01-181-1/+1
| * More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-181-10/+14
| * Fixed a type in $mem model in simlib.vClifford Wolf2014-01-181-1/+1
* | script addedAhmed Irfan2014-01-182-9/+28
* | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-180-0/+0
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| * \ Merge branch 'master' of https://github.com/ahmedirfan1983/yosysAhmed Irfan2014-01-180-0/+0
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| * \ \ Merge branch 'master' of https://github.com/cliffordwolf/yosysAhmed Irfan2014-01-1813-12/+451
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* | | | pmux2muxAhmed Irfan2014-01-187-9/+197
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| * | | Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-181-3/+3
| * | | Added $bu0 cell to simlib.vClifford Wolf2014-01-181-0/+22
| * | | Improved setundef random number generatorClifford Wolf2014-01-181-1/+1
| * | | Added setundef commandClifford Wolf2014-01-172-0/+158
| * | | Some improvements in log_dump_val_worker() templatesClifford Wolf2014-01-171-1/+6
| * | | Added techlibs/common/pmux2mux.vClifford Wolf2014-01-172-1/+26
* | | | verilog default options pullAhmed Irfan2014-01-172-34/+104
* | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-174-7/+119
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| * | | Merge pull request #4 from cliffordwolf/masterAhmed Irfan2014-01-174-7/+119
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| | * | Added verilog_defaults commandClifford Wolf2014-01-171-0/+66
| | * | Added support for $adff with undef data inputs to opt_rmdffClifford Wolf2014-01-171-0/+6
| | * | Added select -assert-none and -assert-anyClifford Wolf2014-01-172-7/+47
* | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-172-0/+117
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| * | | Merge pull request #3 from cliffordwolf/masterAhmed Irfan2014-01-172-0/+117
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| | * Added automatic memid generation to memory_unpack commandClifford Wolf2014-01-171-2/+2
| | * Added memory_unpack commandClifford Wolf2014-01-172-0/+117
* | | slice error correctedAhmed Irfan2014-01-161-5/+5
* | | width issuesAhmed Irfan2014-01-152-65/+88
* | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-154-15/+60
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| * | Merge pull request #2 from cliffordwolf/masterAhmed Irfan2014-01-154-15/+60
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| | * Merge pull request #20 from mschmoelzer/masterClifford Wolf2014-01-141-0/+1
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| | | * Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))Martin Schmölzer2014-01-141-0/+1
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| | * Added hierarchy -libdir optionClifford Wolf2014-01-141-4/+48
| | * renamed LibertyParer to LibertyParserClifford Wolf2014-01-143-9/+9
| | * Added "+" to list of liberty token charactersClifford Wolf2014-01-141-2/+2
* | | BTOR backendAhmed Irfan2014-01-142-279/+334
* | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-147-72/+364
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| * | Merge pull request #1 from cliffordwolf/masterAhmed Irfan2014-01-141-5/+71
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| | * Added "opt_const -mux_undef"Clifford Wolf2014-01-141-5/+71
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| * Fixed typo in frontends/ast/simplify.ccClifford Wolf2014-01-121-1/+1
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