aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Fixed memory_unpack for initialized memoriesClifford Wolf2015-04-291-0/+17
|
* Preserve important attributes in splitnetsClifford Wolf2015-04-291-0/+13
|
* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-294-1/+38
|
* ice40_opt bugfixClifford Wolf2015-04-272-6/+4
|
* iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-271-3/+44
|
* Added simplemap $lut supportClifford Wolf2015-04-273-8/+27
|
* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-273-2/+134
|
* Initialization support for all iCE40 bram modesClifford Wolf2015-04-268-28/+65
|
* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-255-54/+261
|
* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-251-59/+83
|
* Updated ABC to hg rev 779de2de1481Clifford Wolf2015-04-251-1/+1
|
* More iCE40 bram improvementsClifford Wolf2015-04-254-51/+69
|
* Improved attributes API and handling of "src" attributesClifford Wolf2015-04-247-27/+119
|
* iCE40 bram progressClifford Wolf2015-04-242-16/+35
|
* iCE40 bram tests and fixesClifford Wolf2015-04-246-16/+181
|
* Added ice40 bram supportClifford Wolf2015-04-244-1/+192
|
* Fixed memory_share for unconditional write with part select to memoryClifford Wolf2015-04-221-0/+3
|
* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-191-13/+289
|
* Verilog front-end: define `BLACKBOX in -lib modeClifford Wolf2015-04-191-1/+2
|
* added sync reset to ice40 test_ffs.shClifford Wolf2015-04-183-6/+20
|
* Added ice40 test_arithClifford Wolf2015-04-182-0/+13
|
* Added ice40 SB_CARRY supportClifford Wolf2015-04-183-2/+81
|
* don't consider blackbox modules in "sat" commandClifford Wolf2015-04-181-7/+5
|
* Improved handling of init values in opt_rmdffClifford Wolf2015-04-181-11/+9
| | | | based on a patch by Mingyu Gao, user gaomy3832 on github
* Bugfix for $_DFF_?_ in "dff2dffe -direct-match"Clifford Wolf2015-04-171-2/+2
|
* Added mapping of synchronous set/reset to iCE40 flowClifford Wolf2015-04-173-4/+130
|
* Improved "maccmap" help messageClifford Wolf2015-04-161-2/+2
|
* A "#" does start a comment, not a label.Clifford Wolf2015-04-161-0/+3
|
* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-161-2/+2
|
* Fixed "dff2dffe -direct-match"Clifford Wolf2015-04-162-12/+25
|
* Added simple ice40 dff testsClifford Wolf2015-04-163-0/+49
|
* improved ice40 dff cell mappingClifford Wolf2015-04-163-7/+46
|
* Added "dff2dffe -direct-match"Clifford Wolf2015-04-161-14/+35
|
* use "hierarchy -auto-top" in synth_ice40Clifford Wolf2015-04-141-3/+3
|
* more cells in ice40 cell libraryClifford Wolf2015-04-141-8/+289
|
* Added "splice -wires"Clifford Wolf2015-04-131-9/+20
|
* Added handling of bool-output cells to "wreduce"Clifford Wolf2015-04-131-0/+11
|
* Improved xilinx "bram1" testClifford Wolf2015-04-091-1/+2
|
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-092-2/+27
|
* Added back-end auto-detect for .edif and .jsonClifford Wolf2015-04-091-0/+4
|
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-092-7/+12
|
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-093-13/+67
|
* Fixed const2big performance bugClifford Wolf2015-04-091-14/+21
|
* techmap code cleanupClifford Wolf2015-04-091-10/+6
|
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-095-0/+78
|
* Added support for "file names with blanks"Clifford Wolf2015-04-087-33/+43
|
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-082-10/+1
|
* Added %M and %C select operatorsClifford Wolf2015-04-071-1/+38
|
* Added "pmuxtree" commandClifford Wolf2015-04-073-0/+164
|
* Added "chparam -list"Clifford Wolf2015-04-071-0/+21
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-24 04:00:20 +0000