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| * | | | | | | | | | | | | | | | | | | Add MUXCY and XORCY to cells_box.vEddie Hung2019-04-162-0/+15
| * | | | | | | | | | | | | | | | | | | Fix wire numberingEddie Hung2019-04-161-1/+2
| * | | | | | | | | | | | | | | | | | | Do not put constants into output_bitsEddie Hung2019-04-161-2/+2
| * | | | | | | | | | | | | | | | | | | Remove write_verilog callEddie Hung2019-04-161-1/+1
| * | | | | | | | | | | | | | | | | | | Fix spacingEddie Hung2019-04-162-2/+2
| * | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-162-3/+1
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| * | | | | | | | | | | | | | | | | | | | NULL check before useEddie Hung2019-04-161-1/+1
| * | | | | | | | | | | | | | | | | | | | WIP for box supportEddie Hung2019-04-161-36/+93
| * | | | | | | | | | | | | | | | | | | | ABC to read_box before reading netlistEddie Hung2019-04-161-1/+3
| * | | | | | | | | | | | | | | | | | | | Make cells.box whiteboxes not blackboxesEddie Hung2019-04-161-2/+2
| * | | | | | | | | | | | | | | | | | | | read_verilog cells_box.v before techmapEddie Hung2019-04-161-1/+1
| * | | | | | | | | | | | | | | | | | | | synth_xilinx: before abc read +/xilinx/cells_box.vEddie Hung2019-04-161-0/+1
| * | | | | | | | | | | | | | | | | | | | Add +/xilinx/cells_box.v containing models for ABC boxesEddie Hung2019-04-162-0/+11
| * | | | | | | | | | | | | | | | | | | | For 'stat' do not count modules with abc_box_idEddie Hung2019-04-161-0/+3
| * | | | | | | | | | | | | | | | | | | | Do not call abc on modules with abc_box_id attrEddie Hung2019-04-161-0/+3
| * | | | | | | | | | | | | | | | | | | | Revert "Add abc_box_id attribute to MUXF7/F8 cells"Eddie Hung2019-04-161-2/+0
| * | | | | | | | | | | | | | | | | | | | Use abc_box_idEddie Hung2019-04-151-2/+1
| * | | | | | | | | | | | | | | | | | | | Check abc_box_id attrEddie Hung2019-04-151-1/+16
| * | | | | | | | | | | | | | | | | | | | Add abc_box_id attribute to MUXF7/F8 cellsEddie Hung2019-04-151-0/+2
| * | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-159-100/+246
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| * | | | | | | | | | | | | | | | | | | | | PI before CIEddie Hung2019-04-121-2/+2
| * | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-04-121-3/+9
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| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/pmux2shiftx' into xc7muxEddie Hung2019-04-111-1/+0
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| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/pmux2shiftx' into xc7muxEddie Hung2019-04-116-8/+93
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| * | | | | | | | | | | | | | | | | | | | | | | | Fix cells_map.v some moreEddie Hung2019-04-111-7/+7
| * | | | | | | | | | | | | | | | | | | | | | | | More fine tuningEddie Hung2019-04-111-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | | Fix cells_map.vEddie Hung2019-04-111-7/+7
| * | | | | | | | | | | | | | | | | | | | | | | | Fix typoEddie Hung2019-04-111-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | Juggle opt calls in synth_xilinxEddie Hung2019-04-112-30/+35
| * | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-101-1/+1
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| * | | | | | | | | | | | | | | | | | | | | | | | | WIP for cells_map.v -- maybe working?Eddie Hung2019-04-101-32/+27
| * | | | | | | | | | | | | | | | | | | | | | | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1Eddie Hung2019-04-101-31/+38
| * | | | | | | | | | | | | | | | | | | | | | | | | Fix for when B_SIGNED = 1Eddie Hung2019-04-101-1/+8
| * | | | | | | | | | | | | | | | | | | | | | | | | Update doc for synth_xilinxEddie Hung2019-04-101-7/+8
| * | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-101-24/+21
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| * | | | | | | | | | | | | | | | | | | | | | | | | | ff_map.v after abcEddie Hung2019-04-101-5/+5
| * | | | | | | | | | | | | | | | | | | | | | | | | | Tidy upEddie Hung2019-04-101-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | Move map_cells to before map_lutsEddie Hung2019-04-101-11/+12
| * | | | | | | | | | | | | | | | | | | | | | | | | | WIP for $shiftx to wide muxEddie Hung2019-04-101-1/+63
| * | | | | | | | | | | | | | | | | | | | | | | | | | Update LUT delaysEddie Hung2019-04-101-11/+8
| * | | | | | | | | | | | | | | | | | | | | | | | | | Add cells.lut to techlibs/xilinx/Eddie Hung2019-04-092-0/+16
| * | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx to call abc with -lut +/xilinx/cells.lutEddie Hung2019-04-091-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | Add delays to cells.boxEddie Hung2019-04-091-4/+12
| * | | | | | | | | | | | | | | | | | | | | | | | | | Add "-lut <file>" support to abc9Eddie Hung2019-04-091-13/+31
| * | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx with abc9 to use -boxEddie Hung2019-04-091-1/+4
| * | | | | | | | | | | | | | | | | | | | | | | | | | Add techlibs/xilinx/cells.boxEddie Hung2019-04-092-0/+6
| * | | | | | | | | | | | | | | | | | | | | | | | | | Add "-box" option to abc9Eddie Hung2019-04-091-7/+22
| * | | | | | | | | | | | | | | | | | | | | | | | | | Add 'setundef -zero' call prior to aigmap in abc9Eddie Hung2019-04-091-0/+4
| * | | | | | | | | | | | | | | | | | | | | | | | | | Comment outEddie Hung2019-04-091-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-092-1/+14