| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove iterator based Module::remove as per @cliffordwolf | Eddie Hung | 2019-06-18 | 3 | -18/+9 |
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| * | Remove unncessary header | Eddie Hung | 2019-06-18 | 1 | -3/+0 |
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| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-18 | 3 | -3/+15 |
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| | * | Merge pull request #1086 from udif/pr_elab_sys_tasks2 | Clifford Wolf | 2019-06-18 | 2 | -3/+13 |
| | |\ | | | | | | | Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks) | ||||
| | | * | Fixed brojen $error()/$info/$warning() on non-generate blocks | Udi Finkelstein | 2019-06-11 | 2 | -3/+13 |
| | | | | | | | | | | | | | (within always/initial blocks) | ||||
| | * | | Add timescale and generated-by header to yosys-smtbmc MkVcd | Clifford Wolf | 2019-06-16 | 1 | -0/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Really permute Xilinx LUT mappings as default LUT6.I5:A6 | Eddie Hung | 2019-06-18 | 1 | -16/+16 |
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| * | | | Revert "Fix (do not) permute LUT inputs, but permute mux selects" | Eddie Hung | 2019-06-18 | 1 | -33/+31 |
| | | | | | | | | | | | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d. | ||||
| * | | | Clean up | Eddie Hung | 2019-06-18 | 1 | -6/+4 |
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| * | | | Fix (do not) permute LUT inputs, but permute mux selects | Eddie Hung | 2019-06-18 | 1 | -31/+33 |
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| * | | | Fix copy-pasta issue | Eddie Hung | 2019-06-17 | 1 | -9/+8 |
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| * | | | Permute INIT for +/xilinx/lut_map.v | Eddie Hung | 2019-06-17 | 1 | -32/+58 |
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| * | | | Simplify comment | Eddie Hung | 2019-06-17 | 1 | -1/+1 |
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| * | | | Update LUT7/8 delays to take account for [ABC]OUTMUX delay | Eddie Hung | 2019-06-17 | 1 | -5/+5 |
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| * | | | &scorr before &sweep, remove &retime as recommended | Eddie Hung | 2019-06-17 | 1 | -1/+1 |
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| * | | | Copy not move parameters/attributes | Eddie Hung | 2019-06-17 | 1 | -3/+4 |
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| * | | | Fix leak removing cells during ABC integration; also preserve attr | Eddie Hung | 2019-06-17 | 3 | -27/+37 |
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| * | | | Try -W 300 | Eddie Hung | 2019-06-17 | 1 | -1/+2 |
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| * | | | Re-enable &dc2 | Eddie Hung | 2019-06-17 | 1 | -1/+1 |
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| * | | | Cleanup | Eddie Hung | 2019-06-16 | 3 | -299/+33 |
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| * | | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O | Eddie Hung | 2019-06-15 | 1 | -2/+2 |
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| * | | | Leave breadcrumb behind | Eddie Hung | 2019-06-14 | 1 | -0/+2 |
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| * | | | Remove redundant condition | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
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| * | | | Revert "Cleanup/optimise toposort in write_xaiger" | Eddie Hung | 2019-06-14 | 1 | -44/+40 |
| | | | | | | | | | | | | | | | | | | | This reverts commit 1948e7c846ea318d003148974945d917701a4452. Restores old toposort with optimisations | ||||
| * | | | Update comment | Eddie Hung | 2019-06-14 | 1 | -1/+2 |
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| * | | | Check that whiteboxes are synthesisable | Eddie Hung | 2019-06-14 | 1 | -4/+8 |
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| * | | | Get rid of compiler warnings | Eddie Hung | 2019-06-14 | 2 | -7/+7 |
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| * | | | As per @daveshah1 remove async DFF timing from xilinx | Eddie Hung | 2019-06-14 | 1 | -2/+2 |
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| * | | | Cover __APPLE__ too for little to big endian | Eddie Hung | 2019-06-14 | 2 | -8/+16 |
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| * | | | Update abc9 -D doc | Eddie Hung | 2019-06-14 | 1 | -1/+2 |
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| * | | | Enable "abc9 -D <num>" for timing-driven synthesis | Eddie Hung | 2019-06-14 | 1 | -9/+9 |
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| * | | | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 4 | -47/+47 |
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| * | | | Resolve comments from @daveshah1 | Eddie Hung | 2019-06-14 | 3 | -17/+11 |
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| * | | | Add XC7_WIRE_DELAY macro to synth_xilinx.cc | Eddie Hung | 2019-06-14 | 1 | -1/+3 |
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| * | | | Update delays based on SymbiFlow/prjxray-db | Eddie Hung | 2019-06-14 | 1 | -12/+13 |
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| * | | | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} | Eddie Hung | 2019-06-14 | 4 | -3/+3 |
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| * | | | Comment out dist RAM boxing on ECP5 for now | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
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| * | | | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 5 | -79/+79 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-14 | 2 | -0/+46 |
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| | * | | Merge pull request #829 from abdelrahmanhosny/master | Serge Bazanski | 2019-06-13 | 2 | -0/+46 |
| | |\ \ | | |/ | |/| | Dockerfile for Yosys | ||||
| | | * | address review comments | Abdelrahman | 2019-03-01 | 1 | -23/+9 |
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| | | * | add dockerignore file | Abdelrahman | 2019-02-26 | 1 | -0/+13 |
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| | | * | dockerize yosys | Abdelrahman | 2019-02-26 | 1 | -0/+47 |
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| * | | | Make doc consistent | Eddie Hung | 2019-06-14 | 3 | -3/+6 |
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| * | | | Cleanup | Eddie Hung | 2019-06-14 | 1 | -1/+0 |
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| * | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-14 | 8 | -72/+194 |
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| | * \ \ | Merge pull request #1097 from YosysHQ/dave/xaig_ecp5 | Eddie Hung | 2019-06-14 | 8 | -72/+194 |
| | |\ \ \ | | | | | | | | | | | Add ECP5 ABC9 support (to xaig branch) | ||||
| | | * | | | ecp5: Add abc9 option | David Shah | 2019-06-14 | 8 | -72/+194 |
| | |/ / / | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | Cleanup | Eddie Hung | 2019-06-14 | 1 | -7/+3 |
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| * | | | | Cleanup/optimise toposort in write_xaiger | Eddie Hung | 2019-06-14 | 1 | -54/+47 |
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index : iCE40/yosys | |
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