| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -5/+15 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow attributes on individual switch cases in RTLIL | |||||
| | | * | | | | | | | Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire | Clifford Wolf | 2019-07-09 | 1 | -0/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Throw runtime exception when trying to convert inexistend C++ object to Python | |||||
| | | * | | | | | | | Merge pull request #1147 from YosysHQ/clifford/fix1144 | Clifford Wolf | 2019-07-09 | 3 | -82/+26 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve specify dummy parser | |||||
| | | * | | | | | | | Merge pull request #1154 from whitequark/manual-sync-always | Clifford Wolf | 2019-07-09 | 1 | -2/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | manual: explain the purpose of `sync always` | |||||
| | | * | | | | | | | Merge pull request #1153 from YosysHQ/dave/fix_multi_mux | David Shah | 2019-07-09 | 3 | -3/+25 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | memory_dff: Fix checking of feedback mux input when more than one mux | |||||
| | | * | | | | | | | Fix read_verilog assert/assume/etc on default case label, fixes ↵ | Clifford Wolf | 2019-07-09 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | autotest.sh to define _AUTOTB when test_autotb | Eddie Hung | 2019-07-09 | 1 | -1/+1 | |
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| | | * | | | | | | | Merge pull request #1146 from gsomlo/gls-test-abc-ext | Clifford Wolf | 2019-07-09 | 4 | -8/+29 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | tests: use optional ABCEXTERNAL when specified | |||||
| | | * | | | | | | | Checkout yosys-0.9-rc branch of yosys-tests | Eddie Hung | 2019-07-02 | 1 | -1/+1 | |
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| | | * | | | | | | | Add missing CHANGELOG entries | Eddie Hung | 2019-06-28 | 1 | -0/+3 | |
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| | * | | | | | | | | Merge pull request #1112 from acw1251/pyosys_sigsig_issue | Clifford Wolf | 2019-08-25 | 1 | -16/+10 | |
| | |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Fixed pyosys commands returning RTLIL::SigSig | |||||
| | | * | | | | | | | | Fixed pyosys commands returning RTLIL::SigSig | acw1251 | 2019-06-19 | 1 | -16/+10 | |
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| | * | | | | | | | | | Merge pull request #1327 from YosysHQ/clifford/pmgen | Clifford Wolf | 2019-08-24 | 5 | -32/+280 | |
| | |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Add pmgen slices and choices | |||||
| | | * | | | | | | | | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | * | | | | | | | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 | |
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| * | | | | | | | | | | Create new $__XILINX_SHREG_ cell for variable length too | Eddie Hung | 2019-08-23 | 1 | -31/+30 | |
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| * | | | | | | | | | | Do not allow Q of last cell of variable length SRL to be (* keep *) | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
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| * | | | | | | | | | | Also add first.Q to chain_bits since variable length | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
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| * | | | | | | | | | | Do not enforce !EN_POLARITY on $dffe | Eddie Hung | 2019-08-23 | 1 | -2/+0 | |
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| * | | | | | | | | | | Create new cell for fixed length SRL | Eddie Hung | 2019-08-23 | 1 | -14/+22 | |
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| * | | | | | | | | | | Cleanup FDRE matching | Eddie Hung | 2019-08-23 | 1 | -45/+19 | |
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| * | | | | | | | | | | Oops don't need a finally block | Eddie Hung | 2019-08-23 | 1 | -5/+0 | |
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| * | | | | | | | | | | Keep track of bits in variable length chain, to check for taps | Eddie Hung | 2019-08-23 | 1 | -0/+12 | |
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| * | | | | | | | | | | Don't forget $dff has no EN | Eddie Hung | 2019-08-23 | 1 | -2/+4 | |
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| * | | | | | | | | | | Same for variable length | Eddie Hung | 2019-08-23 | 1 | -2/+10 | |
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| * | | | | | | | | | | Filter on en_port for fixed length | Eddie Hung | 2019-08-23 | 1 | -4/+24 | |
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| * | | | | | | | | | | Check clock is consistent | Eddie Hung | 2019-08-23 | 1 | -5/+25 | |
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| * | | | | | | | | | | Fix last_cell.D | Eddie Hung | 2019-08-23 | 1 | -2/+1 | |
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| * | | | | | | | | | | Revert "Add a unique argument to pmgen's nusers()" | Eddie Hung | 2019-08-23 | 1 | -8/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1d88887cfdbeedff7dce9024d8fb4ceb014cb2ef. | |||||
| * | | | | | | | | | | Revert "Fix polarity" | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9cd23cf0feda3e12ceda1f8fa5d28d2b38f2314d. | |||||
| * | | | | | | | | | | Fix polarity | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| * | | | | | | | | | | Check for non unique nusers/fanouts | Eddie Hung | 2019-08-23 | 1 | -2/+2 | |
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| * | | | | | | | | | | Add a unique argument to pmgen's nusers() | Eddie Hung | 2019-08-23 | 1 | -4/+8 | |
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| * | | | | | | | | | | Update doc | Eddie Hung | 2019-08-23 | 1 | -12/+19 | |
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| * | | | | | | | | | | Remove (* init *) entry when consumed into SRL | Eddie Hung | 2019-08-23 | 1 | -2/+6 | |
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| * | | | | | | | | | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| * | | | | | | | | | | Forgot to slice | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| * | | | | | | | | | | Cope with possibility that D could connect to Q on same cell | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| * | | | | | | | | | | Mention shregmap -tech xilinx is superseded | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| * | | | | | | | | | | xilinx_srl now copes with word-level flops $dff{,e} | Eddie Hung | 2019-08-23 | 1 | -8/+3 | |
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| * | | | | | | | | | | xilinx_srl to use 'slice' features of pmgen for word level | Eddie Hung | 2019-08-23 | 2 | -32/+49 | |
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| * | | | | | | | | | | Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 5 | -34/+280 | |
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| | * | | | | | | | | | Fix port hanlding in pmgen | Clifford Wolf | 2019-08-23 | 1 | -4/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | | | Add pmgen slices and choices | Clifford Wolf | 2019-08-23 | 5 | -28/+277 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 9 | -20/+43 | |
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| | * | | | | | | | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | * | | | | | | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 | |
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| | * | | | | | | | Merge pull request #1326 from mmicko/doc-update | Eddie Hung | 2019-08-23 | 1 | -2/+5 | |
| | |\ \ \ \ \ \ \ | | |/ / / / / / | |/| | | | | | | Make macOS dependency clear | |||||
| | | * | | | | | | Make macOS depenency clear | Miodrag Milanovic | 2019-08-23 | 1 | -2/+5 | |
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| | * | | | | / | Do not propagate mem2reg attribute through to result | Eddie Hung | 2019-08-22 | 2 | -1/+3 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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