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* tests: Fix path of yosys invocation in xprop testsJannis Harder2023-02-101-1/+1
| | | | | For now xprop test failures are still expected and ignored, but without this change, they did not even run unless the yosys build was in path.
* Merge pull request #3667 from jix/xprop-test-make-fixJannis Harder2023-02-101-1/+1
|\ | | | | tests: in xprop tests, use MAKE variable if set
| * tests: in xprop tests, use MAKE variable if setJannis Harder2023-02-101-1/+1
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* | Bump versiongithub-actions[bot]2023-02-091-1/+1
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* | Next dev cycleMiodrag Milanovic2023-02-082-2/+5
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* | Release version 0.26Miodrag Milanovic2023-02-082-4/+4
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* | Merge pull request #3662 from YosysHQ/micko/wide_case_select_boxJannis Harder2023-02-082-4/+82
|\ \ | |/ |/| Add Verific import support for OPER_WIDE_CASE_SELECT_BOX
| * For case select values use Sa instead of Sx and SzMiodrag Milanovic2023-02-082-5/+42
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| * Add verific import support for OPER_WIDE_CASE_SELECT_BOXMiodrag Milanovic2023-02-061-0/+41
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* | Updated changelogMiodrag Milanovic2023-02-082-0/+21
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* | Merge pull request #3625 from povik/show_cleanupN. Engelhardt2023-02-061-56/+82
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| * | passes: show: s/pos/bitpos/ for readabilityMartin Povišer2023-01-131-4/+5
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Reuse string parts in generation of portboxesMartin Povišer2023-01-131-2/+5
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Touch chunk iteration in gen_portboxMartin Povišer2023-01-131-8/+11
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Label no_signode flagMartin Povišer2023-01-131-20/+19
| | | | | | | | | | | | | | | | | | Label the flag and rearrange the control flow a bit. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Simplify wire bit range logicMartin Povišer2023-01-131-8/+10
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Factor out 'join_label_pieces'Martin Povišer2023-01-131-20/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In two places, we are joining label pieces by a '|' separator. We go about it by putting the separator behind each entry, then removing the trailing separator in a final fixup pass on the built string. For easier reading, replace those occurrences by a new factored-out 'join_label_pieces' function. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Label signed_suffix flagMartin Povišer2023-01-131-3/+6
| | | | | | | | | | | | | | | | | | To make it easier to follow what's going on. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: s/idx/dot_idx/ for readabilityMartin Povišer2023-01-131-7/+7
| | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | passes: show: Fix portbox bit ranges in case of driven signalsMartin Povišer2023-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the 'show' pass generates portboxes to detail the connection of cell ports to wires, it has special handling of signal chunk repetitions, but those repetitions are not accounted for in the displayed bit range in case of cell outputs. Fix that, and so bring it into consistence with the behavior on cell inputs. So, taking for example the following Verilog snippet, module DRIVER (Q); output [7:0] Q; assign Q = 8'b10101010; endmodule module main; wire w; DRIVER driver(.Q({8{w}})); endmodule make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox instead of '7:7 - 8x 0:0' which it displayed formerly. Signed-off-by: Martin Povišer <povik@cutebit.org>
* | | Bump versiongithub-actions[bot]2023-02-051-1/+1
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* | | Merge pull request #3659 from whitequark/update-abcCatherine2023-02-041-1/+1
|\ \ \ | | | | | | | | Bump ABCREV to fix WASM build
| * | | Bump ABCREV to fix WASM build.Catherine2023-02-041-1/+1
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* | | Bump versiongithub-actions[bot]2023-02-041-1/+1
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* | | backends/firrtl: Ensure `modInstance` is validAki Van Ness2023-02-031-0/+6
| |/ |/| | | | | | | | | | | This should fix #3648 where when calling `emit_elaborated_extmodules` it checks to see if a module is a black-box, however there was no validation that the cell type was actually known, and it just always assumed that we would get a valid instance, causing a segfault.
* | Bump versiongithub-actions[bot]2023-02-021-1/+1
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* | Merge pull request #3655 from jix/smt2_fix_b_op_widthJannis Harder2023-02-011-1/+4
|\ \ | | | | | | smt2: Fix operation width computation for boolean producing cells
| * | smt2: Fix operation width computation for boolean producing cellsJannis Harder2023-02-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The output width for the boolean value should not influence the operation width. The previous incorrect width extension would still produce correct results, but could produce invalid smt2 output for reduction operators when the output width was larger than the width of the vector to which the reduction was applied. This fixes #3654
* | | Bump versiongithub-actions[bot]2023-01-311-1/+1
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* | | Merge pull request #3650 from jix/rtlil_roundtrip_z_bitsJannis Harder2023-01-304-1/+22
|\ \ \ | | | | | | | | backends/rtlil: Do not shorten a value with z bits to 'x
| * | | backends/rtlil: Do not shorten a value with z bits to 'xJannis Harder2023-01-294-1/+22
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* | | add option to fsm_detect to ignore self-resettingN. Engelhardt2023-01-301-7/+22
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* | | add pmux option to bmuxmap for better fsm detection with verific frontendN. Engelhardt2023-01-302-6/+75
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* | | Bump versiongithub-actions[bot]2023-01-301-1/+1
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* | | Resolve struct member package typesDag Lem2023-01-292-0/+11
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* | | Handle struct members of union type (#3641)Dag Lem2023-01-293-2/+18
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* | Bump versiongithub-actions[bot]2023-01-261-1/+1
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* | Merge pull request #3647 from jix/formalff-hierarchy-fixMiodrag Milanović2023-01-251-1/+1
|\ \ | | | | | | formalff: Fix crash with _NOT_ gates in -hierarchy mode
| * | formalff: Fix crash with _NOT_ gates in -hierarchy modeJannis Harder2023-01-251-1/+1
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* | Bump versiongithub-actions[bot]2023-01-241-1/+1
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* | Merge pull request #3624 from jix/sim_ywMiodrag Milanović2023-01-2315-113/+1722
|\ \ | | | | | | Changes to support SBY trace generation with the sim command
| * | sim/formalff: Clock handling for yw cosimJannis Harder2023-01-115-33/+274
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| * | sim: Improvements and fixes for yw cosimJannis Harder2023-01-116-52/+154
| | | | | | | | | | | | | | | | | | * Fixed $cover handling * Improved sparse memory handling when writing traces * JSON summary output
| * | Support for BTOR witness to Yosys witness conversionJannis Harder2023-01-115-20/+312
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| * | aiger: Use new JSON code for writing aiger witness map filesJannis Harder2023-01-113-55/+96
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| * | Add json.{h,cc} for pretty printing JSONJannis Harder2023-01-113-1/+223
| | | | | | | | | | | | | | | | | | Avoids errors in trailing comma handling, broken indentation and improper escaping that is common when building JSON by manually concatenating strings.
| * | sim: New -append option for Yosys witness cosimJannis Harder2023-01-111-5/+14
| | | | | | | | | | | | This is needed to support SBY's append option.
| * | sim: Add Yosys witness (.yw) cosimulationJannis Harder2023-01-111-3/+194
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| * | New kernel/yw.{h,cc} to support reading Yosys witness filesJannis Harder2023-01-113-1/+380
| | | | | | | | | | | | | | | | | | This contains parsing code as well as generic routines to associate the hierarchical signals paths within a Yosys witness file to a loaded RTLIL design, including support for memories.
| * | sim: Only check formal cells during gclk simulation updatesJannis Harder2023-01-111-16/+19
| | | | | | | | | | | | This is required for compatibility with non-multiclock formal semantics.
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