| Commit message (Collapse) | Author | Age | Files | Lines |
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ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
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Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
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Fix solver output parsing for exists-forall optimization
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"sat", "unsat", or "unknown".
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
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Fixes #1804.
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Closes #1762. Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
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options are set.
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Support standard typedef grammar (Fixed)
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fix typo in `write_smt2` help
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Clean up pseudo-private member usage in `passes/sat/miter.cc`.
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ice40: Map unmapped 'mince' DFFs to gate level
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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ice40: Fix typos in SPRAM ABC9 timing specs
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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Fix NDEBUG warnings
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Fixes #1781.
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Add dependency to verilog_lexer.cc
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Add `exec` command to allow running shell commands from inside Yosys scripts
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I hereby assign to Claire Wolf the copyright for all work I did on `passes/cmds/exec.cc`.
In the event that this copyright assignment is not legally valid, I offer this work under the ISC license.
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Co-Authored-By: Miodrag Milanović <mmicko@gmail.com>
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also to specify regexes that must _not_ match.
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Add precise locations for asserts
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Fix make test on macOS: add bash to brewfile & fix argument order
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Default bash on macOS is version 3, which does not support `define -A`, now used in `tests/arch/run-test.sh`. Use brew to install newer bash.
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Clean up code style and pseudo-private member usage in `passes/cmds/select.cc`
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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