aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-213-15/+42
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #885 from YosysHQ/clifford/fix873Clifford Wolf2019-03-191-2/+4
|\ | | | | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #808 from eddiehung/read_aigerEddie Hung2019-03-1935-6/+632
|\ | | | | Add new read_aiger frontend
| * Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-19113-792/+6364
| |\ | |/ |/|
* | Merge pull request #884 from zachjs/masterClifford Wolf2019-03-192-1/+61
|\ \ | | | | | | fix local name resolution in prefix constructs
| * | fix local name resolution in prefix constructsZachary Snow2019-03-182-1/+61
|/ /
* | Update issue templateClifford Wolf2019-03-171-5/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Update issue templateClifford Wolf2019-03-171-0/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #877 from FelixVi/masterClifford Wolf2019-03-161-1/+4
|\ \ | | | | | | Add note about test requirements in README
| * | Add note about test requirements in READMEFelix Vietmeyer2019-03-161-1/+4
|/ /
* | Improve mix of src/wire/wirebit coverage in "mutate -list"Clifford Wolf2019-03-161-29/+84
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #876 from YosysHQ/clifford/fmcombineClifford Wolf2019-03-164-17/+374
|\ \ | | | | | | Add fmcombine pass
| * | Add "fmcombine -fwd -bwd -nop"Clifford Wolf2019-03-151-10/+59
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add fmcombine passClifford Wolf2019-03-154-17/+325
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #875 from YosysHQ/clifford/mutateClifford Wolf2019-03-154-5/+862
|\ \ | | | | | | Add "mutate" pass
| * | Improvements in "mutate" list-reduce algorithmClifford Wolf2019-03-151-13/+36
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "mutate -cfg", improve pick_cover behaviorClifford Wolf2019-03-141-46/+101
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add a strictly coverage-driven mutation selection strategyClifford Wolf2019-03-141-1/+70
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve "mutate" wire coverage metricClifford Wolf2019-03-141-1/+16
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add more mutation types, improve mutation src coverClifford Wolf2019-03-141-92/+268
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix smtbmc.py handling of zero appended stepsClifford Wolf2019-03-141-5/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "mutate" command DB reduce functionalityClifford Wolf2019-03-141-12/+181
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add hashlib "<container>::element(int n)" methodsClifford Wolf2019-03-141-0/+6
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "mutate -mode inv", various other mutate improvementsClifford Wolf2019-03-141-99/+213
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add basic "mutate -list N" frameworkClifford Wolf2019-03-142-0/+230
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Disable realmath testsClifford Wolf2019-03-151-1/+1
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #874 from YosysHQ/clifford/andoptClifford Wolf2019-03-141-0/+7
|\ \ | | | | | | Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
| * | Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327Clifford Wolf2019-03-141-0/+7
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #872 from YosysHQ/clifford/pmuxfixClifford Wolf2019-03-142-1/+10
|\ \ | | | | | | Improve handling of "full_case" attributes
| * | Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix a syntax bug in ilang backend related to process case statementsClifford Wolf2019-03-141-1/+1
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #869 from cr1901/win-shellClifford Wolf2019-03-143-1/+377
|\ \ | | | | | | Install launcher executable when running yosys-smtbmc on Windows.
| * | Install launcher executable when running yosys-smtbmc on Windows.William D. Jones2019-03-133-1/+377
| | | | | | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net>
* | | Merge pull request #868 from YosysHQ/clifford/fixmemClifford Wolf2019-03-132-40/+24
|\ \ \ | | | | | | | | Various mem2reg-related improvements in handling of memories
| * | | Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve handling of memories used in mem index expressions on LHS of an ↵Clifford Wolf2019-03-121-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | assignment Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Remove outdated "blocking assignment to memory" warningClifford Wolf2019-03-121-10/+0
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867Clifford Wolf2019-03-121-6/+8
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix a bug in handling quotes in multi-cmd lines in Yosys scriptsClifford Wolf2019-03-121-1/+7
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #866 from YosysHQ/clifford/idstuffClifford Wolf2019-03-125-5/+71
|\ \ \ | |/ / |/| | Improve determinism of IdString DB for similar scripts
| * | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-115-5/+71
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #864 from YosysHQ/svalabelfixEddie Hung2019-03-112-92/+66
|\ \ \ | |/ / |/| | Fix handling of cases that look like sva labels, fixes #862
| * | Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-102-92/+66
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add ENABLE_GLOB Makefile switchClifford Wolf2019-03-112-3/+10
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
|\ \ | | | | | | iCE40 BRAM primitives init from file
| * | ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| | | | | | | | | | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-14 19:32:45 +0000
pan class="p">, 0)); Report_Handler.Message ("error limit reached"); Report_Handler.Message_End.all; end if; Nbr_Errors := Nbr_Errors + 1; end if; -- Limit the number of errors. if New_Id = Msgid_Error and then Nbr_Errors > Max_Nbr_Errors then return; end if; Report_Handler.Error_Start (Err => (Origin, New_Id, Loc.File, Loc.Line, Loc.Offset, 0)); if In_Group > 0 then In_Group := In_Group + 1; end if; -- Display message. declare First, N : Positive; Argn : Integer; begin N := Msg'First; First := N; Argn := Args'First; while N <= Msg'Last loop if Msg (N) = '%' then Report_Handler.Message (Msg (First .. N - 1)); First := N + 2; pragma Assert (N < Msg'Last); N := N + 1; case Msg (N) is when '%' => Report_Handler.Message ("%"); Argn := Argn - 1; when 'i' => -- Identifier. declare Arg : Earg_Type renames Args (Argn); Id : Name_Id; begin Report_Handler.Message (""""); case Arg.Kind is when Earg_Vhdl_Node => Id := Vhdl.Nodes.Get_Identifier (Arg.Val_Vhdl_Node); when Earg_Id => Id := Arg.Val_Id; when others => -- Invalid conversion to identifier. raise Internal_Error; end case; Report_Handler.Message (Name_Table.Image (Id)); Report_Handler.Message (""""); end; when 'c' => -- Character declare Arg : Earg_Type renames Args (Argn); begin Report_Handler.Message ("'"); case Arg.Kind is when Earg_Char => Report_Handler.Message ((1 => Arg.Val_Char)); when others => -- Invalid conversion to character. raise Internal_Error; end case; Report_Handler.Message ("'"); end; when 't' => -- A token declare Arg : Earg_Type renames Args (Argn); begin case Arg.Kind is when Earg_Vhdl_Token => Report_Vhdl_Token (Arg.Val_Vhdl_Tok); when others => -- Invalid conversion to character. raise Internal_Error; end case; end; when 'l' => -- Location declare Arg : Earg_Type renames Args (Argn); Arg_Loc : Location_Type; Arg_File : Source_File_Entry; Arg_Line : Natural; Arg_Col : Natural; begin case Arg.Kind is when Earg_Location => Arg_Loc := Arg.Val_Loc; when Earg_Vhdl_Node => Arg_Loc := Vhdl.Nodes.Get_Location (Arg.Val_Vhdl_Node); when others => raise Internal_Error; end case; Location_To_Position (Arg_Loc, Arg_File, Arg_Line, Arg_Col); -- Do not print the filename if in the same file as -- the error location. if Arg_File = Loc.File then Report_Handler.Message ("line "); else Report_Handler.Message (Name_Table.Image (Get_File_Name (Arg_File))); Report_Handler.Message (":"); end if; Report_Handler.Message (Natural_Image (Arg_Line)); Report_Handler.Message (":"); Report_Handler.Message (Natural_Image (Arg_Col)); end; when 'n' => -- Node declare Arg : Earg_Type renames Args (Argn); begin case Arg.Kind is when Earg_Vhdl_Node => Report_Handler.Message (Disp_Node (Arg.Val_Vhdl_Node)); when others => -- Invalid conversion to node. raise Internal_Error; end case; end; when 's' => -- String declare Arg : Earg_Type renames Args (Argn); begin Report_Handler.Message (""""); case Arg.Kind is when Earg_String8 => Report_Handler.Message (Str_Table.String_String8 (Arg.Val_Str8.Str, Arg.Val_Str8.Len)); when others => -- Invalid conversion to character. raise Internal_Error; end case; Report_Handler.Message (""""); end; when 'v' => -- Numerical values declare Arg : Earg_Type renames Args (Argn); begin case Arg.Kind is when Earg_Uns32 => declare S : constant String := Uns32'Image (Arg.Val_Uns32); begin Report_Handler.Message (S (2 .. S'Last)); end; when others => raise Internal_Error; end case; end; when others => -- Unknown format. raise Internal_Error; end case; Argn := Argn + 1; end if; N := N + 1; end loop; Report_Handler.Message (Msg (First .. N - 1)); -- Are all arguments displayed ? pragma Assert (Argn > Args'Last); end; Report_Handler.Message_End.all; end Report_Msg; procedure Report_Start_Group is begin pragma Assert (In_Group = 0); In_Group := 1; Report_Handler.Message_Group.all (True); end Report_Start_Group; procedure Report_End_Group is begin pragma Assert (In_Group > 0); In_Group := 0; Report_Handler.Message_Group.all (False); end Report_End_Group; procedure Error_Msg_Option (Msg: String) is begin Report_Msg (Msgid_Error, Option, No_Source_Coord, Msg); end Error_Msg_Option; procedure Warning_Msg_Option (Id : Msgid_Warnings; Msg: String) is begin Report_Msg (Id, Option, No_Source_Coord, Msg); end Warning_Msg_Option; function Make_Earg_Vhdl_Node (V : Vhdl.Nodes.Iir) return Earg_Type is begin return (Kind => Earg_Vhdl_Node, Val_Vhdl_Node => V); end Make_Earg_Vhdl_Node; function Make_Earg_Vhdl_Token (V : Vhdl.Tokens.Token_Type) return Earg_Type is begin return (Kind => Earg_Vhdl_Token, Val_Vhdl_Tok => V); end Make_Earg_Vhdl_Token; end Errorout;
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-14 19:32:45 +0000