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* pass jny: ensured the cell collection is cleared between modulesAki Van Ness2022-04-081-0/+1
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* pass jny: fixed missing quotes around the type value for the cell sortAki Van Ness2022-04-081-1/+1
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* pass jny: fixed the backslash escape for stringsAki Van Ness2022-04-081-2/+1
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* pass jny: removed the invalid json escapesAki Van Ness2022-04-081-12/+0
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* pass jny: added some todo comments about things that need to be done before ↵Aki Van Ness2022-04-081-0/+5
| | | | a proper merge, but it should be enough for the PoC at the moment
* pass jny: changed the constructor initializers to use parens rather than ↵Aki Van Ness2022-04-081-2/+2
| | | | curly-braces to hopefully make GCC 4.8 happy
* pass jny: fixed the string escape method to be less jank and more properAki Van Ness2022-04-081-21/+58
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* pass jny: fixed the signed output for param value outputAki Van Ness2022-04-081-1/+1
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* pass jny: added connection outputAki Van Ness2022-04-081-4/+88
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* pass jny: added filter options for including connections, attributes, and ↵Aki Van Ness2022-04-081-25/+125
| | | | properties
* pass jny: large chunk of refactoring to make the JSON output more pretty and ↵Aki Van Ness2022-04-081-75/+89
| | | | the internals less of a spaghetti nightmare
* metadata -> jny: migrated to the proper name for the passAki Van Ness2022-04-083-21/+19
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* pass metadata: added the machinery to write param and attributesAki Van Ness2022-04-081-8/+27
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* pass metadata: removed superfluous `stringf` callsAki Van Ness2022-04-081-37/+40
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* pass metadata: some more rough work on dumping the parameters and attributesAki Van Ness2022-04-081-6/+6
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* pass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happyAki Van Ness2022-04-081-1/+1
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* pass metadata: added the output of parameters,Aki Van Ness2022-04-081-7/+35
| | | | it's kinda dumb at the moment and needs parsing based on type but it's a start
* pass metadata: fixed some of the output formattingAki Van Ness2022-04-081-0/+3
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* pass metadata: initial commit of the metadata pass for exporting design ↵Aki Van Ness2022-04-082-0/+277
| | | | metadata for yosys assisted tooling
* Bump versiongithub-actions[bot]2022-04-081-1/+1
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* Merge pull request #3269 from YosysHQ/micko/fix_autotopCatherine2022-04-071-13/+13
|\ | | | | Reorder steps in -auto-top to fix synth command, fixes #3261
| * Reorder steps in -auto-top to fix synth command, fixes #3261Miodrag Milanovic2022-04-051-13/+13
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* | abc: Add support for FFs with reset in -dffMarcelina Kościelnicka2022-04-071-90/+229
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* | Bump versiongithub-actions[bot]2022-04-061-1/+1
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* | sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-054-1/+45
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* Next dev cycleMiodrag Milanovic2022-04-052-2/+5
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* Release version 0.16Miodrag Milanovic2022-04-052-3/+3
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* Bump versiongithub-actions[bot]2022-04-051-1/+1
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* show: Fix width labels.Marcelina Kościelnicka2022-04-041-23/+18
| | | | See #3266.
* Update CHANGELOG and manualMiodrag Milanovic2022-04-042-2/+63
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* Merge pull request #3265 from YosysHQ/micko/sim_improvementsMiodrag Milanović2022-04-041-4/+11
|\ | | | | Improve sim by setting proper past D and AD signals
| * past_ad initial value settingMiodrag Milanovic2022-04-021-0/+3
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| * setInitState can be only one altering valuesMiodrag Milanovic2022-04-021-4/+6
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| * Set past_d value for init stateMiodrag Milanovic2022-04-021-0/+2
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* Merge pull request #3264 from jix/invalid_ff_dcinit_mergeJannis Harder2022-04-023-2/+71
|\ | | | | opt_merge: Add `-keepdc` option required for formal verification
| * opt_merge: Add `-keepdc` option required for formal verificationJannis Harder2022-04-013-2/+71
| | | | | | | | | | | | | | | | The `-keepdc` option prevents merging flipflops with dont-care bits in their initial value, as, in general, this is not a valid transform for formal verification. The keepdc option of `opt` is passed along to `opt_merge` now.
* | Bump versiongithub-actions[bot]2022-04-021-1/+1
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* | Merge pull request #3263 from YosysHQ/micko/clk2ff_initMiodrag Milanović2022-04-011-0/+2
|\ \ | |/ |/| Set init values for wrapped async control signals
| * Set init values for wrapped async control signalsMiodrag Milanovic2022-04-011-0/+2
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* Merge pull request #3262 from YosysHQ/micko/verific_hiernetMiodrag Milanović2022-04-011-1/+1
|\ | | | | Preserve internal wires for external nets
| * Preserve internal wires for external netsMiodrag Milanovic2022-04-011-1/+1
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* Bump versiongithub-actions[bot]2022-04-011-1/+1
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* Merge pull request #3256 from YosysHQ/micko/aiw_multiclockMiodrag Milanović2022-03-311-16/+86
|\ | | | | Support memories in aiw and multiclock
| * Support memories in aiw and multiclockMiodrag Milanovic2022-03-311-16/+86
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* Bump versiongithub-actions[bot]2022-03-311-1/+1
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* Merge pull request #3259 from YosysHQ/micko/verific_valgrindMiodrag Milanović2022-03-305-8/+16
|\ | | | | Fix valgrind tests when using verific
| * Fix valgrind tests when using verificMiodrag Milanovic2022-03-305-8/+16
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* | Merge pull request #3260 from YosysHQ/micko/proper_scopenameMiodrag Milanović2022-03-302-9/+4
|\ \ | |/ |/| Proper scope naming from FST
| * Proper scope naming from FSTMiodrag Milanovic2022-03-302-9/+4
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* Merge pull request #3250 from YosysHQ/micko/verific_consistentMiodrag Milanović2022-03-302-23/+27
|\ | | | | Import Verific netlist in consistent order
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