| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | Merge pull request #2416 from QuantamHD/master | whitequark | 2020-10-31 | 1 | -1/+6 | |
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| | * | | | | This patch adds support for defining the ABC location at runtime instead of a... | Ethan Mahintorabi | 2020-10-28 | 1 | -1/+6 | |
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| * | | | | Bump version | Yosys Bot | 2020-10-31 | 1 | -1/+1 | |
| * | | | | Update verific version | Miodrag Milanovic | 2020-10-30 | 1 | -1/+1 | |
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| * | | | Bump version | Yosys Bot | 2020-10-25 | 1 | -1/+1 | |
| * | | | xilinx: Fix attributes_test.ys | Marcelina Kościelnicka | 2020-10-24 | 1 | -4/+2 | |
| * | | | Bump version | Yosys Bot | 2020-10-23 | 1 | -1/+1 | |
| * | | | nexus: Add make_transp to BRAMs | David Shah | 2020-10-22 | 1 | -0/+3 | |
| * | | | Merge pull request #2403 from nakengelhardt/sim_timescale | N. Engelhardt | 2020-10-22 | 1 | -0/+21 | |
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| | * | | | use strftime instead of put_time for gcc 4.8 compatibility | N. Engelhardt | 2020-10-21 | 1 | -4/+5 | |
| | * | | | wild guessing at the problem because it builds fine on my machines | N. Engelhardt | 2020-10-16 | 1 | -0/+3 | |
| | * | | | sim -vcd: add date, version, and option for timescale | N. Engelhardt | 2020-10-16 | 1 | -0/+17 | |
| * | | | | memory_dff: Fix needlessly duplicating enable bits. | Marcelina Kościelnicka | 2020-10-22 | 2 | -0/+32 | |
| * | | | | Bump version | Yosys Bot | 2020-10-22 | 1 | -1/+1 | |
| * | | | | btor: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -93/+102 | |
| * | | | | smt2: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -186/+244 | |
| * | | | | verilog_backend: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -274/+251 | |
| * | | | | sim: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -103/+90 | |
| * | | | | clk2fflogic: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -68/+45 | |
| * | | | | opt_mem: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -81/+6 | |
| * | | | | memory_bram: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -121/+90 | |
| * | | | | memory_map: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -138/+81 | |
| * | | | | memory_unpack: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -106/+10 | |
| * | | | | memory_collect: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -223/+9 | |
| * | | | | memory_nordff: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -63/+9 | |
| * | | | | Add new helper structures to represent memories. | Marcelina Kościelnicka | 2020-10-21 | 3 | -1/+516 | |
| * | | | | Bump version | Yosys Bot | 2020-10-21 | 1 | -1/+1 | |
| * | | | | Merge pull request #2405 from byuccl/fix_xilinx_cells | clairexen | 2020-10-20 | 1 | -2/+2 | |
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| | * | | | | Move signal declarations to before first use | Jeff Goeders | 2020-10-19 | 1 | -2/+2 | |
| * | | | | | Merge pull request #2404 from YosysHQ/claire/fixrpcargs | clairexen | 2020-10-20 | 1 | -1/+2 | |
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| | * | | | | | Fix argument handling in connect_rpc | Claire Xenia Wolf | 2020-10-19 | 1 | -1/+2 | |
| * | | | | | | Bump version | Yosys Bot | 2020-10-20 | 1 | -1/+1 | |
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| * | | | | | Merge pull request #2397 from daveshah1/nexus | Miodrag Milanović | 2020-10-19 | 30 | -0/+12528 | |
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| | * | | | | synth_nexus: Initial implementation | David Shah | 2020-10-15 | 30 | -0/+12528 | |
| * | | | | | Bump version | Yosys Bot | 2020-10-16 | 1 | -1/+1 | |
| * | | | | | Merge pull request #2398 from jakobwenzel/smtbmc-escape | clairexen | 2020-10-15 | 1 | -11/+29 | |
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| | * | | | | | smtbmc: escape identifiers in verilog testbench | Jakob Wenzel | 2020-10-06 | 1 | -11/+29 | |
| * | | | | | | Bump version | Yosys Bot | 2020-10-13 | 1 | -1/+1 | |
| * | | | | | | extend verific library API for formal apps and generators | Miodrag Milanovic | 2020-10-12 | 1 | -15/+83 | |
| * | | | | | | Bump version | Yosys Bot | 2020-10-09 | 1 | -1/+1 | |
| * | | | | | | opt_clean: Better memory handling. | Marcelina Kościelnicka | 2020-10-08 | 2 | -8/+94 | |
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| * | / / / | Bump version | Yosys Bot | 2020-10-06 | 1 | -1/+1 | |
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| * | | | | Update required Verific version | Miodrag Milanović | 2020-10-05 | 1 | -1/+1 | |
| * | | | | Bump version | Yosys Bot | 2020-10-03 | 1 | -1/+1 | |
| * | | | | Merge pull request #2396 from YosysHQ/claire/empty-param | clairexen | 2020-10-02 | 1 | -0/+3 | |
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| | * | | | | Ignore empty parameters in Verilog module instantiations | Claire Xenia Wolf | 2020-10-01 | 1 | -0/+3 | |
| * | | | | | Bump version | Yosys Bot | 2020-10-02 | 1 | -1/+1 | |
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| * | | | | Merge pull request #2378 from udif/pr_dollar_high_low | clairexen | 2020-10-01 | 4 | -31/+159 | |
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| | * | | | | We can now handle array slices (e.g. $size(x[1]) etc. ) | Udi Finkelstein | 2020-09-17 | 2 | -9/+20 | |
| | * | | | | Fixed comments, removed debug message | Udi Finkelstein | 2020-09-16 | 1 | -5/+5 | |
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index : iCE40/yosys | |
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