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* Add optimization of tristate buffer with constant control inputClifford Wolf2018-05-121-0/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "hierarchy -simcheck"Clifford Wolf2018-05-121-7/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Further improve handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-69/+108
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-26/+46
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "#ifdef __FreeBSD__"Johnny Sorocil2018-05-055-9/+52
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* Add ABC FAQ to "help abc"Clifford Wolf2018-05-041-2/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "yosys -e regex" for turning warnings into errorsClifford Wolf2018-05-043-4/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #537 from mithro/yosys-vprClifford Wolf2018-05-044-11/+48
|\ | | | | Improving Yosys when used with VPR
| * Improving vpr output support.Tim 'mithro' Ansell2018-04-184-7/+40
| | | | | | | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
| * synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
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* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-035-21/+58
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Support more character literalsDan Gisselquist2018-05-031-1/+9
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* | Update ABC to git rev f23ea8eClifford Wolf2018-04-301-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_blif -inames -iattr"Clifford Wolf2018-04-151-22/+46
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve Makefile error handling for when abc/ is a hg working copyClifford Wolf2018-04-121-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add PRIM_HDL_ASSERTION support to Verific importerClifford Wolf2018-04-071-3/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $global_clocking in VerificClifford Wolf2018-04-061-1/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add documentation for anyconst/anyseq/allconst/allseq attributeClifford Wolf2018-04-061-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verific anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-2/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "verific -autocover"Clifford Wolf2018-04-062-5/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #530 from makaimann/set-ram-flagsClifford Wolf2018-04-061-0/+3
|\ | | | | Set RAM runtime flags for Verific frontend
| * Set RAM runtime flags for Verific frontendmakaimann2018-04-051-0/+3
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* Added missing dont_use handling for SR FFs to dfflibmapClifford Wolf2018-04-051-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Create issue_template.mdClifford Wolf2018-04-041-0/+16
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* Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constantsClifford Wolf2018-04-041-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed -stbv handling in SMT2 back-endClifford Wolf2018-04-041-1/+1
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* Merge pull request #522 from c60k28/masterClifford Wolf2018-04-0111-178/+233
|\ | | | | Fixed broken Quartus backend on dffeas init value, and other updates.
| * Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵c60k282018-03-3111-178/+233
|/ | | | value for the POWER_UP parameter. Fixed and tested Cyclone V device
* Remove left-over log_ping debug commands.. oops.Clifford Wolf2018-03-311-4/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #521 from azonenberg/for_cliffordClifford Wolf2018-03-314-0/+113
|\ | | | | coolrunner2: Improve optimization for TFF/counters
| * coolrunner2: Add an ANDTERM/XOR between chained FFsRobert Ou2018-03-311-0/+58
| | | | | | | | | | | | | | In some cases (e.g. the low bits of counters) the design might end up with a flip-flop whose input is directly driven by another flip-flop. This isn't possible in the Coolrunner-II architecture, so add a single AND term and XOR in this case.
| * coolrunner2: Split multi-bit netsRobert Ou2018-03-311-0/+1
| | | | | | | | | | The PAR tool doesn't expect any "dangling" nets with no drivers nor sinks. By splitting the nets, clean removes them.
| * coolrunner2: Add extraction for TFFsRobert Ou2018-03-313-0/+54
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* Add smtio status msgs when --progress is inactiveClifford Wolf2018-03-291-2/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in smtio.py VCD file generatorClifford Wolf2018-03-291-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Removed $timescale from "sat" command VCD writerClifford Wolf2018-03-291-1/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Set stack size to at least 128 MB (large stack needed for parsing huge ↵Clifford Wolf2018-03-271-0/+13
| | | | | | expressions) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-273-2/+201
| | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Merge pull request #515 from edcote/patch-1Clifford Wolf2018-03-271-3/+5
|\ | | | | Rename rename to renames
| * Rename rename to renamesEdmond Cote2018-03-201-3/+5
| | | | | | Create TCL alias for rename command. Using renames. Following the same convention as proc -> procs.
* | Chenged "extensions_map" to "extensions_list" in hierarchy.ccClifford Wolf2018-03-271-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #518 from xerpi/masterClifford Wolf2018-03-271-15/+13
|\ \ | | | | | | passes/hierarchy: Reduce code duplication in expand_module
| * | passes/hierarchy: Reduce code duplication in expand_moduleSergi Granell2018-03-271-15/+13
|/ / | | | | | | | | | | This also makes it easier to add new file extensions support. Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
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