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* Added first draft of FIRRTL back-endClifford Wolf2016-11-172-0/+353
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* Cleanups and fixed in write_verilog regarding reg initClifford Wolf2016-11-161-15/+61
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* Added support for hierarchical defparamsClifford Wolf2016-11-155-17/+65
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* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-156-8/+23
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* Merge pull request #268 from AlexDaniel/masterClifford Wolf2016-11-131-34/+27
|\ | | | | Markdownify README
| * Markdownify READMEAleks-Daniel Jakimenko-Aleksejev2016-11-121-34/+27
|/ | | | | This is the first commit in series. There are many other things that could be improved, this is just the first renderable version.
* Minor bugfix in submodClifford Wolf2016-11-091-0/+1
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* Progress in examples/gowin/Clifford Wolf2016-11-085-21/+95
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* Indenting fixes in gowin sim cell libClifford Wolf2016-11-081-20/+28
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* Bugfix in "setundef" passClifford Wolf2016-11-081-2/+7
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* Added examples/gowin/Clifford Wolf2016-11-076-0/+57
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* Implemented "scc -set_attr"Clifford Wolf2016-11-061-22/+32
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* Bugfix in "scc" commandClifford Wolf2016-11-061-9/+11
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* Fixed anonymous genblock object namesClifford Wolf2016-11-041-1/+1
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* Added hex constant support to write_verilogClifford Wolf2016-11-032-5/+63
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* We are now in 0.7+ developmentClifford Wolf2016-11-031-1/+1
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* Yosys 0.7Clifford Wolf2016-11-031-1/+1
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* Bugfix in "hierarchy -check"Clifford Wolf2016-11-021-1/+1
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* Updated command reference in manualClifford Wolf2016-11-021-100/+568
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* Changelog for Yosys 0.7Clifford Wolf2016-11-021-0/+99
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* Added support for fsm_encoding="user"Clifford Wolf2016-11-021-3/+3
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* Added "fsm_expand -full"Clifford Wolf2016-11-022-17/+35
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* Some fixes in handling of signed arraysClifford Wolf2016-11-012-0/+7
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* iCE40 flow is not experimental anymoreClifford Wolf2016-11-011-1/+1
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* Added initial version of "synth_gowin"Clifford Wolf2016-11-014-0/+266
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* Adde "write_verilog -renameprefix -v"Clifford Wolf2016-11-011-5/+23
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* Added support for (single-clock) transparent memories to bram testsClifford Wolf2016-11-012-10/+23
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* Bugfix in fsm_map for FSMs without reset stateClifford Wolf2016-10-251-1/+2
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* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-224-3/+25
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* Added "setparam -type"Clifford Wolf2016-10-191-3/+13
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* No limit for length of lines in BLIF front-endClifford Wolf2016-10-191-1/+7
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* Merge pull request #250 from azonenberg/masterClifford Wolf2016-10-191-4/+35
|\ | | | | Add support for more GreenPak cells (edge detector, delay, pattern generator)
| * Fixed typo in last commitAndrew Zonenberg2016-10-181-1/+1
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| * greenpak4: Added GP_PGEN cell definitionAndrew Zonenberg2016-10-181-0/+21
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| * Added GLITCH_FILTER parameter to GP_DELAYAndrew Zonenberg2016-10-181-3/+2
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| * greenpak4: added model for GP_EDGEDET blockAndrew Zonenberg2016-10-181-0/+10
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| * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-10-184-8/+98
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* | Ignore L_pi nets in "yosys-smtbmc --cex"Clifford Wolf2016-10-181-2/+5
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* | Use init value "2" for all uninitialized FFs in BLIF back-endClifford Wolf2016-10-181-4/+1
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* | Added "yosys-smtbmc --cex <filename>"Clifford Wolf2016-10-171-1/+35
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* | Bugfix in "miter -assert" handling of assumptionsClifford Wolf2016-10-171-2/+2
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* | Added clk2fflogic support for $dffsr and $dlatchClifford Wolf2016-10-171-1/+57
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| * greenpak4: Changed parameters for GP_SYSRESETAndrew Zonenberg2016-10-161-1/+2
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* Improvements and bugfixes in clk2fflogicClifford Wolf2016-10-161-13/+21
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* cleanup in write_smt2 log messages (-bv and -mem are now default)Clifford Wolf2016-10-161-1/+1
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* Build fixes for VS 2015Clifford Wolf2016-10-162-1/+4
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* Some minor build fixes for Visual CClifford Wolf2016-10-143-3/+16
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* Avoid using strcasecmp()Clifford Wolf2016-10-141-2/+21
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* Fixed version string for out-of-tree buildsClifford Wolf2016-10-141-1/+1
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* Added notes about some formal features to READMEClifford Wolf2016-10-141-2/+23
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