aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* verilog: Squash flex-triggered warning.Marcelina Kościelnicka2021-09-131-0/+2
|
* Updates for CHANGELOG (#2997)Miodrag Milanović2021-09-131-48/+126
| | | Added missing changes from git log and group items
* Bump versiongithub-actions[bot]2021-09-111-1/+1
|
* Merge pull request #3001 from YosysHQ/claire/sigcheckMiodrag Milanović2021-09-102-6/+14
|\ | | | | Add additional check to SigSpec
| * Add additional check to SigSpecClaire Xenia Wolf2021-09-102-6/+14
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* yosys-smtbmc: Fix reused loop variable.Marcelina Kościelnicka2021-09-101-4/+4
| | | | Fixes #2999.
* Bump versiongithub-actions[bot]2021-09-101-1/+1
|
* abc9: make re-entrant (#2993)Eddie Hung2021-09-093-9/+29
| | | | | | | | | * Add testcase * Cleanup some state at end of abc9 * Re-assign abc9_box_id from scratch * Suppress delete unless prep_bypass did something
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-092-1/+15
| | | | | * Add testcase * holes module to instantiate cells with NEW_ID
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-093-7/+30
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* Bump versiongithub-actions[bot]2021-09-031-1/+1
|
* update required verific versionMiodrag Milanovic2021-09-021-1/+1
|
* Bump versiongithub-actions[bot]2021-09-011-1/+1
|
* sv: support declaration in generate for initializationZachary Snow2021-08-319-1/+209
| | | | | | | | This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
* Bump versiongithub-actions[bot]2021-08-311-1/+1
|
* sv: support declaration in procedural for initializationZachary Snow2021-08-305-1/+104
| | | | | In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
* Bump versiongithub-actions[bot]2021-08-301-1/+1
|
* [ECP5] fix wrong link for syn_* attributes description (#2984)kittennbfive2021-08-292-2/+2
|
* Bump versiongithub-actions[bot]2021-08-231-1/+1
|
* Add DLLDELDECP5-PCIe2021-08-221-0/+9
|
* opt_merge: Remove and reinsert init when connecting nets.Marcelina Kościelnicka2021-08-221-3/+4
| | | | | | | | Mutating the SigMap by adding a new connection will throw off FfInitVals index. Work around this by removing the relevant init values from index whenever we connect nets, then re-add the new init value. Should fix #2920.
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-222-2/+26
| | | | | | | | | | Previously, opt_clean would reconnect all ports (including FF Q ports) to a "canonical" SigBit chosen by complex rules, but would leave the init attribute on the old wire. This change applies the same canonicalization rules to the init attributes, ensuring that init moves to wherever the Q port moved. Part of another jab at #2920.
* Bump versiongithub-actions[bot]2021-08-211-1/+1
|
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-205-7/+15
| | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
* Merge pull request #2973 from YosysHQ/micko/optional_extensionsMiodrag Milanović2021-08-202-2/+12
|\ | | | | Make Verific extensions optional
| * Make Verific extensions optionalMiodrag Milanovic2021-08-202-2/+12
|/
* Bump versiongithub-actions[bot]2021-08-181-1/+1
|
* ice40: Fix typo in SB_CARRY specify for LP/UltraPlusSylvain Munaut2021-08-171-2/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Bump versiongithub-actions[bot]2021-08-171-1/+1
|
* kernel/mem: Remove old parameter when upgrading $mem to $mem_v2.Marcelina Kościelnicka2021-08-161-0/+1
| | | | Fixes #2967.
* Bump versiongithub-actions[bot]2021-08-151-1/+1
|
* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-142-40/+47
| | | | Fixes #2962.
* Bump versiongithub-actions[bot]2021-08-141-1/+1
|
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-1311-3/+312
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-144-0/+146
| | | | If all of us are wide, then none of us are!
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-1411-11/+269
| | | | This unlocks wide port recognition by default.
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-134-7/+1355
|
* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-134-2/+319
|
* Merge pull request #2932 from YosysHQ/mwk/logger-check-expectedMiodrag Milanović2021-08-132-5/+14
|\ | | | | logger: Add -check-expected subcommand.
| * logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-122-5/+14
| | | | | | | | | | This allows us to have multiple "expect this warning" calls in a single long script, covering only as many passes as necessary.
* | sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-123-11/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - User-defined types must be data types. Using a net type (e.g. wire) is a syntax error. - User-defined types without a net type are always variables (i.e. logic). - Nets and variables can now be explicitly declared using user-defined types: typedef logic [1:0] W; wire W w; typedef logic [1:0] V; var V v; Fixes #2846
* | Bump versiongithub-actions[bot]2021-08-131-1/+1
| |
* | memory_share: Pass addresses through sigmap_xmux everywhere.Marcelina Kościelnicka2021-08-131-20/+25
|/ | | | This fixes wide port recognition in some cases.
* Bump versiongithub-actions[bot]2021-08-121-1/+1
|
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
| | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-114-8/+55
|
* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-113-14/+24
|
* Add v2 memory cells.Marcelina Kościelnicka2021-08-1122-206/+631
|
* Bump versiongithub-actions[bot]2021-08-111-1/+1
|
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-118-118/+408
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 13:27:59 +0000